`timescale 1ns/1ns

module testbench ();

	parameter cycle = 20;
	parameter half  = 10;

	reg		CLK;
	reg		CLR;
	reg		PB;
	wire [3:0]	LED;
	
	
	niosv_led_c10lp fpga (
		.CLK	(CLK),
		.CLR	(CLR),
		.PB		(PB),
		.LED	(LED)
		);
	
	initial begin
		#0		CLK <= 1'b0;
	end
	
	always begin
		#(half)	CLK <= ~CLK;
	end
	
		
	initial begin
		#0				CLR <= 1'b1;
		#(cycle * 1000)	CLR <= 1'b0;
		#(cycle * 5000)	CLR <= 1'b1;	
	end
				
	initial begin
		#0				PB <= 1'b1;
	end
	
	always begin
		#(cycle * 60000)	PB <= 1'b1;
		#(cycle * 20000)	PB <= 1'b0;
		#(cycle * 30000)	PB <= 1'b1;
	end
	
	
endmodule