library ieee;
use ieee.std_logic_1164.all; 

entity niosv_led_c10lp is
	port
	(
		CLK	:	in  std_logic;
		CLR	:	in  std_logic;
		PB	:	in  std_logic;
		LED	: 	out std_logic_vector(3 downto 0)
	);
end niosv_led_c10lp;

architecture rtl of niosv_led_c10lp is 

	component niosv_system is
		port (
			clk_clk					: in  std_logic := '0';
			reset_reset_n				: in  std_logic := '1';
			pb_pio_export	: in  std_logic := '1';
			led_pio_export	: out std_logic_vector(3 downto 0)        
		);
	end component;


signal	wire_led	:  std_logic_vector(3 downto 0);

begin

niosv: niosv_system
port map	(
	clk_clk					=> CLK,
	reset_reset_n				=> CLR,
	pb_pio_export	=> PB,
	led_pio_export	=> wire_led
	);
	
LED <= not wire_led;

end rtl;