library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture sim of testbench is 

constant	t : time	:= 100 ns;

signal	PB	 : std_logic;
signal	LED	 : std_logic;

component presspb_led
port (
	PB : in std_logic;
	LED : out std_logic
	);
end component;

begin 
	u1 : presspb_led
		port map (
			PB => PB,
			LED => LED
			);
push : process begin
		PB <= '1';
		wait for t *1000;
		PB <= '0';
		wait for t * 5000;
		PB <= '1';
		wait for t * 7000;
		PB <= '0';
		wait for t * 3000;
		PB <= '1';
		wait;
	end process push;
		
end sim;