Agilex™ 3 and Agilex™ 5 FPGAs & SoCs External Memory Interface (EMIF) Schematic Checklist

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Design FPGA/CPLD/ASIC Memory Altera Corporation

Memory-related connections vary depending on the device and protocol, which can be confusing and prone to errors.
This document is intended to show proper memory connections and clarify any questions that may arise when reviewing the schematic.

Target Devices: Agilex™ 3 and Agilex™ 5 FPGAs & SoCs
Supported memory topologies: DDR4/LPDDR4/DDR5/LPDDR5

1. DDR4 (Agilex™ 5 FPGA & SoC)

2. LPDDR4 (Agilex™ 3 and Agilex™ 5 FPGAs & SoCs)

3. DDR5 (Agilex™ 5 FPGA & SoC)

4. LPDDR5 (Agilex™ 5 FPGA & SoC)

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Agilex™ 3 & 5 FPGAs & SoCs External Memory Interface (EMIF) Schematic Checklist (rev.1.0)

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