# Reading pref.tcl
# do C:/Users/12801/Downloads/Radiant_Seminar_ond/Sample/Lab1/sim1/sim1.mdo
# Loading project sim1
# Model Technology ModelSim - Lattice FPGA Edition vlog 2021.4 Compiler 2021.10 Oct 14 2021
# Start time: 14:39:15 on Nov 11,2022
# vlog -reportprogress 300 "+incdir+"C:/Users/12801/Downloads/Radiant_Seminar_ond/Sample/Lab1/MULT/rtl"" -work work C:/Users/12801/Downloads/Radiant_Seminar_ond/Sample/Lab1/MULT/rtl/MULT.v 
# -- Compiling module MULT
# -- Compiling module MULT_ipgen_lscc_multiplier
# -- Compiling module MULT_ipgen_lscc_multiplier_lut
# -- Compiling module MULT_ipgen_lscc_multiplier_dsp
# 
# Top level modules:
# 	MULT
# End time: 14:39:15 on Nov 11,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Lattice FPGA Edition vlog 2021.4 Compiler 2021.10 Oct 14 2021
# Start time: 14:39:15 on Nov 11,2022
# vlog -reportprogress 300 "+incdir+"C:/Users/12801/Downloads/Radiant_Seminar_ond/Sample/Lab1/RAM_DP1/rtl"" -work work C:/Users/12801/Downloads/Radiant_Seminar_ond/Sample/Lab1/RAM_DP1/rtl/RAM_DP1.v 
# -- Compiling module RAM_DP1
# -- Compiling module RAM_DP1_ipgen_lscc_ram_dp
# -- Compiling module RAM_DP1_ipgen_lscc_ram_dp_main
# -- Compiling module RAM_DP1_ipgen_lscc_ram_dp_core
# 
# Top level modules:
# 	RAM_DP1
# End time: 14:39:16 on Nov 11,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Lattice FPGA Edition vlog 2021.4 Compiler 2021.10 Oct 14 2021
# Start time: 14:39:16 on Nov 11,2022
# vlog -reportprogress 300 "+incdir+"C:/Users/12801/Downloads/Radiant_Seminar_ond/Sample/Lab1/PLL1/rtl"" -work work C:/Users/12801/Downloads/Radiant_Seminar_ond/Sample/Lab1/PLL1/rtl/PLL1.v 
# -- Compiling module PLL1
# -- Compiling module PLL1_ipgen_lscc_pll
# -- Compiling module PLL1_ipgen_lscc_apb2lmmi
# 
# Top level modules:
# 	PLL1
# End time: 14:39:16 on Nov 11,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Lattice FPGA Edition vlog 2021.4 Compiler 2021.10 Oct 14 2021
# Start time: 14:39:16 on Nov 11,2022
# vlog -reportprogress 300 "+incdir+"C:/Users/12801/Downloads/Radiant_Seminar_ond/Sample/Lab1/source/impl_1"" -work work C:/Users/12801/Downloads/Radiant_Seminar_ond/Sample/Lab1/source/impl_1/Lab1.v 
# -- Compiling module Lab1
# ** Warning: C:/Users/12801/Downloads/Radiant_Seminar_ond/Sample/Lab1/source/impl_1/Lab1.v(57): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
# 
# Top level modules:
# 	Lab1
# End time: 14:39:16 on Nov 11,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
# Model Technology ModelSim - Lattice FPGA Edition vlog 2021.4 Compiler 2021.10 Oct 14 2021
# Start time: 14:39:16 on Nov 11,2022
# vlog -reportprogress 300 "+incdir+"C:/Users/12801/Downloads/Radiant_Seminar_ond/Sample/Lab1/source/impl_1"" -work work C:/Users/12801/Downloads/Radiant_Seminar_ond/Sample/Lab1/source/impl_1/tb_Lab1.v 
# -- Compiling module Lab1_tf
# 
# Top level modules:
# 	Lab1_tf
# End time: 14:39:16 on Nov 11,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vsim -voptargs="+acc" -lib work -L pmi_work -L ovi_lfmxo5 Lab1_tf 
# Start time: 14:39:20 on Nov 11,2022
# //  ModelSim - Lattice FPGA Edition 2021.4 Oct 14 2021
# //
# //  Copyright 1991-2021 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  ModelSim - Lattice FPGA Edition and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# Loading work.Lab1_tf
# Loading work.Lab1
# Loading sv_std.std
# Loading ovi_lfmxo5.OSCA
# Loading ovi_lfmxo5.OSC_CORE
# Loading ovi_lfmxo5.osc_jedi
# Loading ovi_lfmxo5.osc_digital
# Loading ovi_lfmxo5.stop
# Loading ovi_lfmxo5.osc_analog
# Loading ovi_lfmxo5.VHI
# Loading ovi_lfmxo5.VLO
# Loading work.PLL1
# Loading work.PLL1_ipgen_lscc_pll
# Loading work.RAM_DP1
# Loading work.RAM_DP1_ipgen_lscc_ram_dp
# Loading work.RAM_DP1_ipgen_lscc_ram_dp_main
# Loading work.MULT
# Loading work.MULT_ipgen_lscc_multiplier
# Loading ovi_lfmxo5.GSR
# Loading ovi_lfmxo5.GSR_CORE
# Loading ovi_lfmxo5.gsr_center
# Loading ovi_lfmxo5.PLL
# Loading ovi_lfmxo5.PLL_CORE
# Loading ovi_lfmxo5.gpll_pll_lmmi
# Loading ovi_lfmxo5.gpll_core
# Loading ovi_lfmxo5.gpll_lmmi_pinshorter
# Loading ovi_lfmxo5.lmmis_clkrst
# Loading ovi_lfmxo5.gen_cell_clk_gate
# Loading ovi_lfmxo5.gen_cell_clk_mux21
# Loading ovi_lfmxo5.gen_cell_latr
# Loading ovi_lfmxo5.rstSync
# Loading ovi_lfmxo5.lmmis_fsm
# Loading work.RAM_DP1_ipgen_lscc_ram_dp_core
# Loading work.MULT_ipgen_lscc_multiplier_dsp
# Loading ovi_lfmxo5.PDP16K
# Loading ovi_lfmxo5.PDP16K_MODE
# Loading ovi_lfmxo5.EBR_CORE
# Loading ovi_lfmxo5.ebr_hw
# Loading ovi_lfmxo5.ebr_inbuf
# Loading ovi_lfmxo5.ebr_polctl
# Loading ovi_lfmxo5.ebr_tdp
# Loading ovi_lfmxo5.ebr_pwrsw_vcc
# Loading ovi_lfmxo5.ebr_pwrup
# Loading ovi_lfmxo5.ebr_fbuf
# Loading ovi_lfmxo5.ebr_cfg_in
# Loading ovi_lfmxo5.fifo_new
# ** Warning: (vsim-3015) [PCDPC] - Port size (<protected>) does not match connection size (<protected>) for <protected>.<protected>
#    Time: 0 fs  Iteration: 0  Protected: /Lab1_tf/UUT/i_PLL1/lscc_pll_inst/gen_no_refclk_mon/u_PLL/PLL_inst/<protected> File: nofile Line: 196
# .main_pane.wave.interior.cs.body.pw.wf
# illegal lmmi_mfgout2_sel
# illegal lmmi_mfgout1_sel
# illegal lmmi_mfgout2_sel
# illegal lmmi_mfgout1_sel
# lmmi_ref_integer_mode must be set to 1 for proper PLL functionality
# ** Warning: lmmi_fbk_mmd_dig and lmmi_fbk_mask is equal to 0
#    Time: 2 ns  Scope: Lab1_tf.UUT.i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst.<protected>.<protected> File: nofile Line: 96
# ** Warning: lmmi_ref_mmd_dig and lmmi_ref_mask is equal to 0
#    Time: 2 ns  Scope: Lab1_tf.UUT.i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst.<protected>.<protected> File: nofile Line: 96
# Compile of MULT.v was successful.
# Compile of RAM_DP1.v was successful.
# Compile of PLL1.v was successful.
# Compile of Lab1.v was successful with warnings.
# Compile of tb_Lab1.v was successful.
# 5 compiles, 0 failed with no errors.
vsim -voptargs=+acc -lib work -L pmi_work -L ovi_lfmxo5 work.Lab1_tf
# End time: 14:40:45 on Nov 11,2022, Elapsed time: 0:01:25
# Errors: 0, Warnings: 12
# vsim -voptargs="+acc" -lib work -L pmi_work -L ovi_lfmxo5 work.Lab1_tf 
# Start time: 14:40:45 on Nov 11,2022
# Loading work.Lab1_tf
# Loading work.Lab1
# Loading sv_std.std
# Loading ovi_lfmxo5.OSCA
# Loading ovi_lfmxo5.OSC_CORE
# Loading ovi_lfmxo5.osc_jedi
# Loading ovi_lfmxo5.osc_digital
# Loading ovi_lfmxo5.stop
# Loading ovi_lfmxo5.osc_analog
# Loading ovi_lfmxo5.VHI
# Loading ovi_lfmxo5.VLO
# Loading work.PLL1
# Loading work.PLL1_ipgen_lscc_pll
# Loading work.RAM_DP1
# Loading work.RAM_DP1_ipgen_lscc_ram_dp
# Loading work.RAM_DP1_ipgen_lscc_ram_dp_main
# Loading work.MULT
# Loading work.MULT_ipgen_lscc_multiplier
# Loading ovi_lfmxo5.GSR
# Loading ovi_lfmxo5.GSR_CORE
# Loading ovi_lfmxo5.gsr_center
# Loading ovi_lfmxo5.PLL
# Loading ovi_lfmxo5.PLL_CORE
# Loading ovi_lfmxo5.gpll_pll_lmmi
# Loading ovi_lfmxo5.gpll_core
# Loading ovi_lfmxo5.gpll_lmmi_pinshorter
# Loading ovi_lfmxo5.lmmis_clkrst
# Loading ovi_lfmxo5.gen_cell_clk_gate
# Loading ovi_lfmxo5.gen_cell_clk_mux21
# Loading ovi_lfmxo5.gen_cell_latr
# Loading ovi_lfmxo5.rstSync
# Loading ovi_lfmxo5.lmmis_fsm
# Loading work.RAM_DP1_ipgen_lscc_ram_dp_core
# Loading work.MULT_ipgen_lscc_multiplier_dsp
# Loading ovi_lfmxo5.PDP16K
# Loading ovi_lfmxo5.PDP16K_MODE
# Loading ovi_lfmxo5.EBR_CORE
# Loading ovi_lfmxo5.ebr_hw
# Loading ovi_lfmxo5.ebr_inbuf
# Loading ovi_lfmxo5.ebr_polctl
# Loading ovi_lfmxo5.ebr_tdp
# Loading ovi_lfmxo5.ebr_pwrsw_vcc
# Loading ovi_lfmxo5.ebr_pwrup
# Loading ovi_lfmxo5.ebr_fbuf
# Loading ovi_lfmxo5.ebr_cfg_in
# Loading ovi_lfmxo5.fifo_new
# ** Warning: (vsim-3015) [PCDPC] - Port size (<protected>) does not match connection size (<protected>) for <protected>.<protected>
#    Time: 0 fs  Iteration: 0  Protected: /Lab1_tf/UUT/i_PLL1/lscc_pll_inst/gen_no_refclk_mon/u_PLL/PLL_inst/<protected> File: nofile Line: 196
add wave -position end  sim:/Lab1_tf/ROM_OUT_SIM
run
# illegal lmmi_mfgout2_sel
# illegal lmmi_mfgout1_sel
# illegal lmmi_mfgout2_sel
# illegal lmmi_mfgout1_sel
# lmmi_ref_integer_mode must be set to 1 for proper PLL functionality
# ** Warning: lmmi_fbk_mmd_dig and lmmi_fbk_mask is equal to 0
#    Time: 2 ns  Scope: Lab1_tf.UUT.i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst.<protected>.<protected> File: nofile Line: 96
# ** Warning: lmmi_ref_mmd_dig and lmmi_ref_mask is equal to 0
#    Time: 2 ns  Scope: Lab1_tf.UUT.i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst.<protected>.<protected> File: nofile Line: 96
quit
# End time: 14:41:31 on Nov 11,2022, Elapsed time: 0:00:46
# Errors: 0, Warnings: 4
