| Project Settings |
|---|
| Project Name | proj_1 | Device Name | impl_1: Lattice LFMXO5 : LFMXO5_25 |
| Implementation Name | impl_1 | Top Module | Lab1 |
| Pipelining | 1 | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 1000 |
| Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0 |
| Clock Conversion | 0 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
171 |
81 |
0 |
- |
00m:14s |
- |
2022/11/11
17:05:32 |
| (premap) | Complete |
15 |
62 |
0 |
0m:02s |
0m:02s |
182MB |
2022/11/11
17:05:41 |
| (fpga_mapper) | Complete |
22 |
4 |
0 |
0m:11s |
0m:11s |
219MB |
2022/11/11
17:05:53 |
| Multi-srs Generator |
Complete | | | | 00m:01s | | | 2022/11/11
17:05:34 |
| Area Summary |
|---|
|
| Register bits | 507 |
I/O cells | 41 |
| Block RAMs
(v_ram) | 4 |
DSPs
(dsp_used) | 0 |
| LUTs
(total_luts) | 546 |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| Lab1|jtck_inferred_clock | 200.0 MHz | 225.0 MHz | 0.555 |
| clk48m | 48.0 MHz | 244.7 MHz | 16.747 |
| rvltck | 30.0 MHz | NA | NA |
| System | 200.0 MHz | 350.3 MHz | 2.145 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 2 / 0 |
| |
|