Synthesis Report Synthesis options: The -a option is LFMXO5. The -t option is BBG400. The -sp option is 8_High-Performance_1.0V. The -p option is LFMXO5-25. ########################################################## ### Lattice Family : LFMXO5 ### Device : LFMXO5-25 ### Package : BBG400 ### Performance Grade : 8_High-Performance_1.0V INFO - synthesis: User-Selected Strategy Settings Optimization goal = Timing Top-level module name = Lab1. Target frequency = 200.000000 MHz. Maximum fanout = 1000. Timing path count = 3 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = Auto Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = yes Output HDL file name = Lab1_impl_1.vm. ROM style = auto RAM style = auto The -comp option is TRUE. The -syn option is FALSE. Hardtimer checking is enabled (default). The -dt option is not used. -path C:/Users/12801/Downloads/Radiant_Seminar_ond/Sample/Lab1 (searchpath added) -path C:/Users/12801/Downloads/Radiant_Seminar_ond/Sample/Lab1/MULT (searchpath added) -path C:/Users/12801/Downloads/Radiant_Seminar_ond/Sample/Lab1/PLL1 (searchpath added) -path C:/Users/12801/Downloads/Radiant_Seminar_ond/Sample/Lab1/RAM_DP1 (searchpath added) -path C:/Users/12801/Downloads/Radiant_Seminar_ond/Sample/Lab1/impl_1 (searchpath added) -path C:/lscc/radiant/3.2/ispfpga/jd5f00/data (searchpath added) Mixed language design Verilog design file = C:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.v Verilog design file = C:/Users/12801/Downloads/Radiant_Seminar_ond/Sample/Lab1/source/impl_1/Lab1.v Verilog design file = C:/Users/12801/Downloads/Radiant_Seminar_ond/Sample/Lab1/PLL1/rtl/PLL1.v Verilog design file = C:/Users/12801/Downloads/Radiant_Seminar_ond/Sample/Lab1/RAM_DP1/rtl/RAM_DP1.v Verilog design file = C:/Users/12801/Downloads/Radiant_Seminar_ond/Sample/Lab1/MULT/rtl/MULT.v VHDL library = pmi VHDL design file = C:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.vhd The -r option is OFF. [ Remove LOC Properties is OFF. ] Compile design. Compile Design Begin Analyzing Verilog file c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.v. VERI-1482 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.v(1): analyzing included file c:/lscc/radiant/3.2/ip/pmi/pmi_addsub.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_addsub.v(40): analyzing included file c:/lscc/radiant/3.2/ip/pmi/../common/adder_subtractor/rtl/lscc_add_sub.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.v(2): analyzing included file c:/lscc/radiant/3.2/ip/pmi/pmi_add.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_add.v(50): analyzing included file c:/lscc/radiant/3.2/ip/pmi/../common/adder/rtl/lscc_adder.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.v(3): analyzing included file c:/lscc/radiant/3.2/ip/pmi/pmi_complex_mult.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_complex_mult.v(52): analyzing included file c:/lscc/radiant/3.2/ip/pmi/../common/complex_mult/rtl/lscc_complex_mult.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.v(4): analyzing included file c:/lscc/radiant/3.2/ip/pmi/pmi_counter.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_counter.v(39): analyzing included file c:/lscc/radiant/3.2/ip/pmi/../common/counter/rtl/lscc_cntr.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.v(5): analyzing included file c:/lscc/radiant/3.2/ip/pmi/pmi_distributed_dpram.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_distributed_dpram.v(43): analyzing included file c:/lscc/radiant/3.2/ip/pmi/../common/distributed_dpram/rtl/lscc_distributed_dpram.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.v(6): analyzing included file c:/lscc/radiant/3.2/ip/pmi/pmi_distributed_spram.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_distributed_spram.v(42): analyzing included file c:/lscc/radiant/3.2/ip/pmi/../common/distributed_spram/rtl/lscc_distributed_spram.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.v(7): analyzing included file c:/lscc/radiant/3.2/ip/pmi/pmi_distributed_rom.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_distributed_rom.v(42): analyzing included file c:/lscc/radiant/3.2/ip/pmi/../common/distributed_rom/rtl/lscc_distributed_rom.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.v(8): analyzing included file c:/lscc/radiant/3.2/ip/pmi/pmi_distributed_shift_reg.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_distributed_shift_reg.v(41): analyzing included file c:/lscc/radiant/3.2/ip/pmi/../common/ram_shift_reg/rtl/lscc_shift_register.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.v(9): analyzing included file c:/lscc/radiant/3.2/ip/pmi/pmi_fifo.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_fifo.v(44): analyzing included file c:/lscc/radiant/3.2/ip/pmi/../avant/fifo/rtl/lscc_fifo.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.v(10): analyzing included file c:/lscc/radiant/3.2/ip/pmi/pmi_fifo_dc.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_fifo_dc.v(47): analyzing included file c:/lscc/radiant/3.2/ip/pmi/../avant/fifo_dc/rtl/lscc_fifo_dc.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.v(11): analyzing included file c:/lscc/radiant/3.2/ip/pmi/pmi_mac.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_mac.v(52): analyzing included file c:/lscc/radiant/3.2/ip/pmi/../common/mult_accumulate/rtl/lscc_mult_accumulate.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.v(12): analyzing included file c:/lscc/radiant/3.2/ip/pmi/pmi_multaddsubsum.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_multaddsubsum.v(53): analyzing included file c:/lscc/radiant/3.2/ip/pmi/../common/mult_add_sub_sum/rtl/lscc_mult_add_sub_sum.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.v(13): analyzing included file c:/lscc/radiant/3.2/ip/pmi/pmi_multaddsub.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_multaddsub.v(52): analyzing included file c:/lscc/radiant/3.2/ip/pmi/../common/mult_add_sub/rtl/lscc_mult_add_sub.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.v(14): analyzing included file c:/lscc/radiant/3.2/ip/pmi/pmi_mult.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_mult.v(51): analyzing included file c:/lscc/radiant/3.2/ip/pmi/../common/multiplier/rtl/lscc_multiplier.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.v(15): analyzing included file c:/lscc/radiant/3.2/ip/pmi/pmi_ram_dp.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_ram_dp.v(48): analyzing included file c:/lscc/radiant/3.2/ip/pmi/../avant/ram_dp/rtl/lscc_ram_dp.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.v(16): analyzing included file c:/lscc/radiant/3.2/ip/pmi/pmi_ram_dp_be.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_ram_dp_be.v(49): analyzing included file c:/lscc/radiant/3.2/ip/pmi/../avant/ram_dp/rtl/lscc_ram_dp.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.v(17): analyzing included file c:/lscc/radiant/3.2/ip/pmi/pmi_ram_dp_true.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_ram_dp_true.v(49): analyzing included file c:/lscc/radiant/3.2/ip/pmi/../avant/ram_dp_true/rtl/lscc_ram_dp_true.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.v(18): analyzing included file c:/lscc/radiant/3.2/ip/pmi/pmi_ram_dq.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_ram_dq.v(45): analyzing included file c:/lscc/radiant/3.2/ip/pmi/../avant/ram_dq/rtl/lscc_ram_dq.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.v(19): analyzing included file c:/lscc/radiant/3.2/ip/pmi/pmi_ram_dq_be.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_ram_dq_be.v(45): analyzing included file c:/lscc/radiant/3.2/ip/pmi/../avant/ram_dq/rtl/lscc_ram_dq.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.v(20): analyzing included file c:/lscc/radiant/3.2/ip/pmi/pmi_rom.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_rom.v(45): analyzing included file c:/lscc/radiant/3.2/ip/pmi/../avant/rom/rtl/lscc_rom.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.v(21): analyzing included file c:/lscc/radiant/3.2/ip/pmi/pmi_sub.v. VERI-1328 INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_sub.v(50): analyzing included file c:/lscc/radiant/3.2/ip/pmi/../common/subtractor/rtl/lscc_subtractor.v. VERI-1328 Analyzing Verilog file c:/users/12801/downloads/radiant_seminar_ond/sample/lab1/source/impl_1/lab1.v. VERI-1482 WARNING - synthesis: c:/users/12801/downloads/radiant_seminar_ond/sample/lab1/source/impl_1/lab1.v(57): literal value truncated to fit in 26 bits. VERI-1208 Analyzing Verilog file c:/users/12801/downloads/radiant_seminar_ond/sample/lab1/pll1/rtl/pll1.v. VERI-1482 Analyzing Verilog file c:/users/12801/downloads/radiant_seminar_ond/sample/lab1/ram_dp1/rtl/ram_dp1.v. VERI-1482 Analyzing Verilog file c:/users/12801/downloads/radiant_seminar_ond/sample/lab1/mult/rtl/mult.v. VERI-1482 Analyzing VHDL file c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.vhd. VHDL-1481 Analyzing VHDL file c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.vhd INFO - synthesis: c:/lscc/radiant/3.2/ip/pmi/pmi_lfmxo5.vhd(4): analyzing package components. VHDL-1014 INFO - synthesis: The default VHDL library search path is now "C:/Users/12801/Downloads/Radiant_Seminar_ond/Sample/Lab1/impl_1". VHDL-1504 Top module language type = Verilog. Top module name (Verilog, mixed language): Lab1 INFO - synthesis: c:/users/12801/downloads/radiant_seminar_ond/sample/lab1/source/impl_1/lab1.v(1): compiling module Lab1. VERI-1018 INFO - synthesis: C:/lscc/radiant/3.2/ispfpga/../cae_library/synthesis/verilog/LFMXO5.v(2118): compiling module OSCA(HF_CLK_DIV="19"). VERI-1018 INFO - synthesis: c:/users/12801/downloads/radiant_seminar_ond/sample/lab1/pll1/rtl/pll1.v(11): compiling module PLL1. VERI-1018 INFO - synthesis: c:/users/12801/downloads/radiant_seminar_ond/sample/lab1/pll1/rtl/pll1.v(159): compiling module PLL1_ipgen_lscc_pll(FVCO=1488.0,CLKI_FREQ=24.0,CLKOP_FREQ_ACTUAL=48.0,PLL_RST=1,LOCK_EN=1,FBCLK_DIVIDER_ACTUAL_STR="2",DIVOP_ACTUAL_STR="30",DIVOS_ACTUAL_STR="7",DIVOS2_ACTUAL_STR="7",DIVOS3_ACTUAL_STR="7",DIVOS4_ACTUAL_STR="7",DIVOS5_ACTUAL_STR="7",SSC_N_CODE_STR="0b000000010",DELA="30",DELB="7",DELC="7",DELD="7",DELE="7",DELF="7",IPI_CMP="0b1001",CSET="8P",CRIPPLE="7P",IPP_CTRL="0b0110",IPP_SEL="0b0111",BW_CTL_BIAS="0b1111",V2I_PP_RES="10P7K"). VERI-1018 INFO - synthesis: C:/lscc/radiant/3.2/ispfpga/../cae_library/synthesis/verilog/LFMXO5.v(2863): compiling module PLL(BW_CTL_BIAS="0b1111",CRIPPLE="7P",CSET="8P",DELA="30",DELB="7",DELC="7",DELD="7",DELE="7",DELF="7",DIVA="30",DIVB="7",DIVC="7",DIVD="7",DIVE="7",DIVF="7",ENCLK_CLKOP="ENABLED",V2I_1V_EN="ENABLED",FBK_INTEGER_MODE="ENABLED",FBK_MASK="0b00000000",FBK_MMD_DIG="2",IPI_CMP="0b1001",IPP_CTRL="0b0110",IPP_SEL="0b0111",KP_VCO=" .... P_ICTRL="0b11111",V2I_PP_RES="10P7K",SEL_FBK="FBKCLK0",DIV_DEL=72'b01100000110001000110000001100000011000100110001001100010011000100110000,SIM_FLOAT_PRECISION="0.1"). VERI-1018 INFO - synthesis: c:/users/12801/downloads/radiant_seminar_ond/sample/lab1/ram_dp1/rtl/ram_dp1.v(11): compiling module RAM_DP1. VERI-1018 INFO - synthesis: c:/users/12801/downloads/radiant_seminar_ond/sample/lab1/ram_dp1/rtl/ram_dp1.v(251): compiling module RAM_DP1_ipgen_lscc_ram_dp(MEM_ID="RAM_DP1",MEM_SIZE="18,128",FAMILY="LFMXO5",WADDR_DEPTH=128,WADDR_WIDTH=7,RADDR_DEPTH=128,RADDR_WIDTH=7,INIT_FILE="C:/Users/12801/Downloads/Radiant_Seminar_ond/Sample/Lab1/RAM_DP1/misc/Lab1_RAM_DP1_copy.mem",INIT_MODE="mem_file",BYTE_ENABLE=0,BYTE_WIDTH=1,INIT_VALUE_00="0x0000800008000080000 .... 0000000000000000000000000000000000000000000000000000000000000000",INIT_VALUE_3F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"). VERI-1018 INFO - synthesis: c:/users/12801/downloads/radiant_seminar_ond/sample/lab1/ram_dp1/rtl/ram_dp1.v(653): compiling module RAM_DP1_ipgen_lscc_ram_dp_main(MEM_ID="RAM_DP1",MEM_SIZE="18,128",FAMILY="LIFCL",WADDR_DEPTH=128,WADDR_WIDTH=7,RADDR_DEPTH=128,RADDR_WIDTH=7,INIT_FILE="C:/Users/12801/Downloads/Radiant_Seminar_ond/Sample/Lab1/RAM_DP1/misc/Lab1_RAM_DP1_copy.mem",INIT_MODE="mem_file",BYTE_ENABLE=0,BYTE_SIZE=9,BYTE_WIDTH=1,INIT_VALUE_00="0x000 .... 0000000000000000000000000000000000000000000000000000000000000000",INIT_VALUE_3F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"). VERI-1018 INFO - synthesis: c:/users/12801/downloads/radiant_seminar_ond/sample/lab1/ram_dp1/rtl/ram_dp1.v(4178): compiling module RAM_DP1_ipgen_lscc_ram_dp_core(MEM_ID="RAM_DP1",MEM_SIZE="18,128",FAMILY="LIFCL",DATA_WIDTH_W=32'b010010,DATA_WIDTH_R=32'b010010,INIT_MODE="mem_file",BYTE_ENABLE=1'b0,POSx=32'b0,POSy=32'b0,INIT_VALUE_00="0x000080000800008000080000800008000083FDF8000000000000000000000000000000000007FDFF",INIT_VALUE_01="0x008000080803DF000800 .... T_VALUE_78="0x00",INIT_VALUE_79="0x00",INIT_VALUE_7A="0x00",INIT_VALUE_7B="0x00",INIT_VALUE_7C="0x00",INIT_VALUE_7D="0x00",INIT_VALUE_7E="0x00",INIT_VALUE_7F="0x00"). VERI-1018 INFO - synthesis: C:/lscc/radiant/3.2/ispfpga/../cae_library/synthesis/verilog/LFMXO5.v(2155): compiling module PDP16K(DATA_WIDTH_W="X18",DATA_WIDTH_R="X18",OUTREG="USED",INITVAL_00="0x000080000800008000080000800008000083FDF8000000000000000000000000000000000007FDFF",INITVAL_01="0x008000080803DF0008000080000800000000000000018005F0008080080800808005F00000000000",INITVAL_02="0x00808005F00000000000035F8000000000000000008000080803DF000800 .... 9C038FC05DEC0ADE40B5C00400000000038F0031C00F580",INITVAL_07="0x7FDFF000000000000000000000000000000000000000000000000000000000000040000A5C40DDEC",INIT_DATA="DYNAMIC"). VERI-1018 INFO - synthesis: c:/users/12801/downloads/radiant_seminar_ond/sample/lab1/mult/rtl/mult.v(11): compiling module MULT. VERI-1018 INFO - synthesis: c:/users/12801/downloads/radiant_seminar_ond/sample/lab1/mult/rtl/mult.v(99): compiling module MULT_ipgen_lscc_multiplier(COEFF=2,A_WIDTH=3,B_WIDTH=3,IMPL="DSP",FAMILY="LFMXO5"). VERI-1018 INFO - synthesis: c:/users/12801/downloads/radiant_seminar_ond/sample/lab1/mult/rtl/mult.v(455): compiling module MULT_ipgen_lscc_multiplier_dsp(USE_COEFF=0,A_WIDTH=3,B_WIDTH=3). VERI-1018 LSE: Compile Design done