@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: MO111 :"c:\users\12801\downloads\radiant_seminar_ond\sample\lab1\impl_1\reveal_workspace\tmpreveal\lab1_rvl_top.v":8595:22:8595:33|Tristate driver apb_prdata_o_1 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) on net apb_prdata_o_1 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\12801\downloads\radiant_seminar_ond\sample\lab1\impl_1\reveal_workspace\tmpreveal\lab1_rvl_top.v":8595:22:8595:33|Tristate driver apb_prdata_o_2 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) on net apb_prdata_o_2 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\12801\downloads\radiant_seminar_ond\sample\lab1\impl_1\reveal_workspace\tmpreveal\lab1_rvl_top.v":8595:22:8595:33|Tristate driver apb_prdata_o_3 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) on net apb_prdata_o_3 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\12801\downloads\radiant_seminar_ond\sample\lab1\impl_1\reveal_workspace\tmpreveal\lab1_rvl_top.v":8595:22:8595:33|Tristate driver apb_prdata_o_4 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) on net apb_prdata_o_4 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\12801\downloads\radiant_seminar_ond\sample\lab1\impl_1\reveal_workspace\tmpreveal\lab1_rvl_top.v":8595:22:8595:33|Tristate driver apb_prdata_o_5 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) on net apb_prdata_o_5 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\12801\downloads\radiant_seminar_ond\sample\lab1\impl_1\reveal_workspace\tmpreveal\lab1_rvl_top.v":8595:22:8595:33|Tristate driver apb_prdata_o_6 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) on net apb_prdata_o_6 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\12801\downloads\radiant_seminar_ond\sample\lab1\impl_1\reveal_workspace\tmpreveal\lab1_rvl_top.v":8595:22:8595:33|Tristate driver apb_prdata_o_7 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) on net apb_prdata_o_7 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\12801\downloads\radiant_seminar_ond\sample\lab1\impl_1\reveal_workspace\tmpreveal\lab1_rvl_top.v":8595:22:8595:33|Tristate driver apb_prdata_o_8 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) on net apb_prdata_o_8 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\12801\downloads\radiant_seminar_ond\sample\lab1\impl_1\reveal_workspace\tmpreveal\lab1_rvl_top.v":8593:16:8593:27|Tristate driver apb_pready_o (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) on net apb_pready_o (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\12801\downloads\radiant_seminar_ond\sample\lab1\impl_1\reveal_workspace\tmpreveal\lab1_rvl_top.v":8594:16:8594:28|Tristate driver apb_pslverr_o (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) on net apb_pslverr_o (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) has its enable tied to GND.
@N: FX1184 |Applying syn_allowed_resources blockrams=80 on top level netlist Lab1 
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
