@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: MO111 :"c:\users\12801\downloads\radiant_seminar_ond\sample\lab1\impl_1\reveal_workspace\tmpreveal\lab1_rvl_top.v":8595:22:8595:33|Tristate driver apb_prdata_o_1 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) on net apb_prdata_o_1 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\12801\downloads\radiant_seminar_ond\sample\lab1\impl_1\reveal_workspace\tmpreveal\lab1_rvl_top.v":8595:22:8595:33|Tristate driver apb_prdata_o_2 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) on net apb_prdata_o_2 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\12801\downloads\radiant_seminar_ond\sample\lab1\impl_1\reveal_workspace\tmpreveal\lab1_rvl_top.v":8595:22:8595:33|Tristate driver apb_prdata_o_3 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) on net apb_prdata_o_3 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\12801\downloads\radiant_seminar_ond\sample\lab1\impl_1\reveal_workspace\tmpreveal\lab1_rvl_top.v":8595:22:8595:33|Tristate driver apb_prdata_o_4 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) on net apb_prdata_o_4 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\12801\downloads\radiant_seminar_ond\sample\lab1\impl_1\reveal_workspace\tmpreveal\lab1_rvl_top.v":8595:22:8595:33|Tristate driver apb_prdata_o_5 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) on net apb_prdata_o_5 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\12801\downloads\radiant_seminar_ond\sample\lab1\impl_1\reveal_workspace\tmpreveal\lab1_rvl_top.v":8595:22:8595:33|Tristate driver apb_prdata_o_6 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) on net apb_prdata_o_6 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\12801\downloads\radiant_seminar_ond\sample\lab1\impl_1\reveal_workspace\tmpreveal\lab1_rvl_top.v":8595:22:8595:33|Tristate driver apb_prdata_o_7 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) on net apb_prdata_o_7 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\12801\downloads\radiant_seminar_ond\sample\lab1\impl_1\reveal_workspace\tmpreveal\lab1_rvl_top.v":8595:22:8595:33|Tristate driver apb_prdata_o_8 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) on net apb_prdata_o_8 (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\12801\downloads\radiant_seminar_ond\sample\lab1\impl_1\reveal_workspace\tmpreveal\lab1_rvl_top.v":8594:16:8594:28|Tristate driver apb_pslverr_o (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) on net apb_pslverr_o (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\12801\downloads\radiant_seminar_ond\sample\lab1\impl_1\reveal_workspace\tmpreveal\lab1_rvl_top.v":8593:16:8593:27|Tristate driver apb_pready_o (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) on net apb_pready_o (in view: work.PLL1_ipgen_lscc_pll_uniq_1_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO231 :"c:\users\12801\downloads\radiant_seminar_ond\sample\lab1\impl_1\reveal_workspace\tmpreveal\lab1_rvl_top.v":145:4:145:9|Found counter in view:work.Lab1(verilog) instance led_cont[25:0] 
@N: MO231 :"c:\users\12801\downloads\radiant_seminar_ond\sample\lab1\impl_1\reveal_workspace\tmpreveal\lab1_rvl_top.v":137:4:137:9|Found counter in view:work.Lab1(verilog) instance freq_cont[9:0] 
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT615 |Found clock clk48m with period 20.83ns 
@N: MT615 |Found clock rvltck with period 33.33ns 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
