Copyright (c) 2002-2022 Lattice Semiconductor Corporation, All rights reserved. Fri Nov 11 17:06:03 2022 Command Line: par -w -n 1 -t 1 -s 1 -cores 1 -exp parPathBased=ON \ Lab1_impl_1_map.udb Lab1_impl_1.udb Cost Table Summary Level/ Number Worst Timing Worst Timing Run Run Cost [udb] Unrouted Slack Score Slack(hold) Score(hold) Time Status ---------- -------- ----- ------ ----------- ----------- ---- ------ 5_1 * 0 16.041 0 0.165 0 24 Completed * : Design saved. Total (real) run time for 1-seed: 25 secs par done! Lattice Place and Route Report for Design "Lab1_impl_1_map.udb" Fri Nov 11 17:06:03 2022 Best Par Run PAR: Place And Route Radiant Software (64-bit) 3.2.1.217.3. Command Line: par -w -t 1 -cores 1 -exp parPathBased=ON Lab1_impl_1_map.udb \ Lab1_impl_1_par.dir/5_1.udb Loading Lab1_impl_1_map.udb ... Loading device for application GENERIC from file 'jd5f25.nph' in environment: C:/lscc/radiant/3.2/ispfpga. Package Status: Preliminary Version 7. Performance Hardware Data Status: Preliminary Version 1.6. Design: Lab1 Family: LFMXO5 Device: LFMXO5-25 Package: BBG400 Performance Grade: 8_High-Performance_1.0V WARNING - par: Unable to find the instance/port 'SW[3]' in the constraint 'ldc_set_location -site {T4} [get_ports {SW[3]}]' WARNING - par: In the constraint 'ldc_set_location -site {T4} [get_ports {SW[3]}]', the locate object is not specified WARNING - par: Top module port 'SW[3]' does not connect to anything. Device SLICE utilization summary after final SLICE packing: SLICE 927/11520 8% used WARNING - par: Unable to find the instance/port 'SW[3]' in the constraint 'ldc_set_location -site {T4} [get_ports {SW[3]}]' WARNING - par: In the constraint 'ldc_set_location -site {T4} [get_ports {SW[3]}]', the locate object is not specified WARNING - par: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets. WARNING - par: Unable to find the instance/port 'SW[3]' in the constraint 'ldc_set_location -site {T4} [get_ports {SW[3]}]' WARNING - par: In the constraint 'ldc_set_location -site {T4} [get_ports {SW[3]}]', the locate object is not specified Number of Signals: 1406 Number of Connections: 4382 Device utilization summary: GSR 1/1 100% used VHI 1/1 100% used EBR 4/80 5% used MULT9 1/40 2% used REG18 1/40 2% used PREADD9 1/40 2% used SEIO33 45/299 15% used 45/251 17% bonded OSC 1/1 100% used PLL 1/2 50% used CONFIG_JTAG 1/1 100% used SLICE 927/11520 8% used LUT 715/23040 3% used REG 556/23040 2% used Pin Constraint Summary: 41 out of 45 pins locked (91% locked). Starting Placer Phase 0 (HIER). CPU time: 4 secs , REAL time: 6 secs .......... Finished Placer Phase 0 (HIER). CPU time: 5 secs , REAL time: 6 secs Starting Placer Phase 1. CPU time: 5 secs , REAL time: 6 secs .. .. ..................... Placer score = 338699. Finished Placer Phase 1. CPU time: 13 secs , REAL time: 15 secs Starting Placer Phase 2. . Placer score = 337380 Finished Placer Phase 2. CPU time: 13 secs , REAL time: 15 secs After final PLC packing legalization, all 0 SLICEs that were not satisfying 1 CLK/CE/LSR per HALF-PLC restriction are all placed into compatible PLCs. Clock Report Global Clock Resources: CLK_PIN : 0 out of 26 (0%) PLL : 1 out of 2 (50%) DCS : 0 out of 1 (0%) DCC : 0 out of 62 (0%) ECLKDIV : 0 out of 8 (0%) PCLKDIV : 0 out of 1 (0%) OSC : 1 out of 1 (100%) Global Clocks: PRIMARY "MON_c[0]" from HFCLKOUT on comp "i_OSCA.OSCA_inst" on site "OSC_CORE_R1C59", clk load = 1, ce load = 0, sr load = 0 PRIMARY "clk48m[0]" from CLKOP on comp "i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst" on PLL site "PLL_ULC", clk load = 233, ce load = 0, sr load = 0 PRIMARY "jtck" from JTCK on comp "jtaghub_inst.jtagg_u" on site "TCONFIG_JTAG_CORE38", clk load = 287, ce load = 0, sr load = 0 PRIMARY : 3 out of 16 (18%) Edge Clocks: No edge clock selected. I/O Usage Summary (final): 45 out of 299 (15.1%) SEIO33 sites used. 45 out of 251 (17.9%) bonded SEIO33 sites used. Number of SEIO33 comps: 45; differential: 0 Number of Vref pins used: 0 0 out of 48 (0.0%) SEIO18 sites used. 0 out of 48 (0.0%) bonded SEIO18 sites used. Number of SEIO18 comps: 0; differential: 0 0 out of 24 (0.0%) DIFFIO18 sites used. 0 out of 24 (0.0%) bonded DIFFIO18 sites used. Number of DIFFIO18 comps: 0; differential: 0 I/O Bank Usage Summary: +----------+----------------+------------+------------+------------+ | I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | +----------+----------------+------------+------------+------------+ | 0 | 5 / 40 ( 12%) | 3.3V | - | - | | 1 | 12 / 36 ( 33%) | 3.3V | - | - | | 2 | 21 / 31 ( 67%) | 3.3V | - | - | | 3 | 0 / 32 ( 0%) | - | - | - | | 4 | 0 / 24 ( 0%) | - | - | - | | 5 | 0 / 24 ( 0%) | - | - | - | | 6 | 0 / 24 ( 0%) | - | - | - | | 7 | 3 / 24 ( 12%) | 3.3V | - | - | | 8 | 4 / 32 ( 12%) | 3.3V | - | - | | 9 | 0 / 32 ( 0%) | - | - | - | +----------+----------------+------------+------------+------------+ Total Placer CPU time: 13 secs , REAL time: 15 secs Writing design to file Lab1_impl_1_par.dir/5_1.udb ... WARNING - par: Unable to find the instance/port 'SW[3]' in the constraint 'ldc_set_location -site {T4} [get_ports {SW[3]}]' WARNING - par: In the constraint 'ldc_set_location -site {T4} [get_ports {SW[3]}]', the locate object is not specified Start NBR router at 17:06:18 11/11/22 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in timing report. You should always run the timing tool to verify your design. ***************************************************************** Starting routing resource preassignment INFO - par: The external feedback signal clk48m[0] for PLL_CORE instance i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst will use the primary clock network. Preassignment Summary: -------------------------------------------------------------------------------- 359 connections routed with dedicated routing resources 3 global clock signals routed 969 connections routed (of 4382 total) (22.11%) --------------------------------------------------------- Clock routing summary: Primary clocks (6 used out of 32 available): Signal "jtck" (4, 20) Clock loads: 287 out of 287 routed (100.00%) Signal "clk48m[0]" (7, 23) Clock loads: 233 out of 233 routed (100.00%) Signal "MON_c[0]" (3, 19) Clock loads: 1 out of 1 routed (100.00%) Data loads: 0 out of 1 routed ( 0.00%) --------------------------------------------------------- -------------------------------------------------------------------------------- Completed routing resource preassignment WARNING - par: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets. Start NBR section for initial routing at 17:06:21 11/11/22 Level 4, iteration 1 580(0.05%) conflicts; 3413(77.89%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 15.712ns/0.000ns; real time: 4 secs Level 4, iteration 2 158(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 15.829ns/0.000ns; real time: 4 secs Info: Initial congestion level at 75.00% usage is 0 Info: Initial congestion area at 75.00% usage is 0 (0.00%) Start NBR section for normal routing at 17:06:23 11/11/22 Level 4, iteration 1 132(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 15.829ns/0.000ns; real time: 5 secs Level 4, iteration 2 91(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 15.829ns/0.000ns; real time: 5 secs Level 4, iteration 3 32(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 15.957ns/0.000ns; real time: 5 secs Level 4, iteration 4 16(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 15.957ns/0.000ns; real time: 5 secs Level 4, iteration 5 8(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 15.935ns/0.000ns; real time: 5 secs Level 4, iteration 6 3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 15.935ns/0.000ns; real time: 5 secs Level 4, iteration 7 3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 15.935ns/0.000ns; real time: 5 secs Level 4, iteration 8 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 15.935ns/0.000ns; real time: 5 secs Start NBR section for setup/hold timing optimization with effort level 3 at 17:06:23 11/11/22 Starting full timing analysis... Start NBR section for post-routing at 17:06:25 11/11/22 End NBR router with 0 unrouted connection WARNING - par: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets. Starting full timing analysis... NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Estimated worst slack<setup> : 16.041ns Estimated worst slack<hold > : 0.165ns Timing score<setup> : 0 Timing score<hold > : 0 Number of connections with timing violations<setup> : 0 (0.00%) Number of connections with timing violations<hold > : 0 (0.00%) ----------- Total CPU time 8 secs Total REAL time: 9 secs Completely routed. End of route. 4382 routed (100.00%); 0 unrouted. Writing design to file Lab1_impl_1_par.dir/5_1.udb ... All signals are completely routed. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Worst slack<setup/<ns>> = 16.041 PAR_SUMMARY::Timing score<setup/<ns>> = 0.000 PAR_SUMMARY::Worst slack<hold /<ns>> = 0.165 PAR_SUMMARY::Timing score<hold /<ns>> = 0.000 PAR_SUMMARY::Number of errors = 0 Total CPU Time: 23 secs Total REAL Time: 25 secs Peak Memory Usage: 411.35 MB par done! Note: user must run 'timing' for timing closure signoff. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2022 Lattice Semiconductor Corporation, All rights reserved.