Lattice Mapping Report File for Design Module 'Lab1_impl_1' Target Vendor: LATTICE Target Device: LFMXO5-25BBG400 Target Performance: 8_High-Performance_1.0V Mapper: version Radiant Software (64-bit) 3.2.1.217.3 Mapped on: Fri Nov 11 17:06:01 2022 Design Information Command line: map -i Lab1_impl_1_syn.udb -pdc C:/Users/12801/Downloads/Radiant _Seminar_ond/Sample/Lab1/source/impl_1/Lab1.pdc -o Lab1_impl_1_map.udb -mp Lab1_impl_1.mrp -hierrpt -gui Design Summary Number of registers: 556 out of 23937 (2%) Number of SLICE registers: 556 out of 23040 (2%) Number of PIO Input registers: 0 out of 299 (0%) Number of PIO Output registers: 0 out of 299 (0%) Number of PIO Tri-State registers: 0 out of 299 (0%) Number of LUT4s: 715 out of 23040 (3%) Number used as logic LUT4s: 577 Number used as distributed RAM: 0 (6 per 16X4 RAM) Number used as ripple logic: 138 (2 per CCU2) Number of PIOs used/reserved: 48 out of 299 (15%) Number of PIOs reserved: 3 (per sysConfig and/or prohibit constraint) Number of PIOs used: 45 Number of PIOs used for single ended IO: 45 Number of PIO pairs used for differential IO: 0 Number allocated to regular speed PIOs: 45 out of 251 (18%) Number allocated to high speed PIOs: 0 out of 48 (0%) Number of Dedicated IO used for ADC: 0 out of 4 (0%) Number of IDDR/ODDR/TDDR functions used: 0 out of 646 (0%) Number of IOs using at least one DDR function: 0 (0 differential) Number of Block RAMs: 4 out of 80 (5%) Number of Large RAMs: 0 out of 1 (0%) Number of Logical DSP Functions: Number of Pre-Adders (9+9): 0 out of 40 (0%) Number of Multipliers (18x18): 0.5 out of 20 (2%) Number of 9X9: 1 (1 18x18 = 2 9x9) Number of 18x18: 0 (1 18x18 = 1 18x18) Number of 18x36: 0 (2 18x18 = 1 18x36) Number of 36x36: 0 (4 18x18 = 1 36x36) Number of 54-bit Accumulators: 0 out of 10 (0%) Number of 18-bit Registers: 1 out of 40 (2%) Number of Physical DSP Components: Number of PREADD9: 1 out of 40 (2%) Used PREADD9: 0 Bypassed PREADD9: 1 Number of MULT9: 1 out of 40 (2%) Used MULT9: 1 Bypassed MULT9: 0 Number of MULT18: 0 out of 20 (0%) Number of MULT18X36: 0 out of 10 (0%) Number of MULT36: 0 out of 5 (0%) Number of ACC54: 0 out of 10 (0%) Number of REG18: 1 out of 40 (2%) Used REG18: 1 Bypassed REG18: 0 Number of PLLs: 1 out of 2 (50%) Number of DDRDLLs: 0 out of 2 (0%) Number of DLLDELs: 0 out of 8 (0%) Number of DQSs: 0 out of 4 (0%) Number of DCSs: 0 out of 1 (0%) Number of DCCs: 0 out of 62 (0%) Number of PCLKDIVs: 0 out of 1 (0%) Number of ECLKDIVs: 0 out of 8 (0%) Number of ECLKSYNCs: 0 out of 8 (0%) Number of ADC Blocks: 0 out of 1 (0%) Number of SGMIICDRs: 0 out of 2 (0%) Number of PMUs: 0 out of 1 (0%) Number of BNKREF18s: 0 out of 2 (0%) Number of BNKREF33s: 0 out of 8 (0%) Number of I2CFIFOs: 0 out of 1 (0%) Number of Oscillators: 1 out of 1 (100%) Number of GSR: 1 out of 1 (100%) Number of Cryptographic Block: 0 out of 1 (0%) Number of Config IP: 0 out of 1 (0%) TSALL: 0 out of 1 (0%) Number of JTAG: 1 out of 1 (100%) Number of SED: 0 out of 1 (0%) Number of Clocks: 4 Net jtck: 287 loads, 0 rising, 287 falling (Driver: Pin jtaghub_inst.jtagg_u/JTCK) Net jtaghub_inst.tck: 1 loads, 1 rising, 0 falling (Driver: Port TCK) Net clk48m[0]: 232 loads, 232 rising, 0 falling (Driver: Pin i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP) Net MON_c[0]: 1 loads, 1 rising, 0 falling (Driver: Pin i_OSCA.OSCA_inst/HFCLKOUT) Number of Clock Enables: 46 Net VCC: 4 loads, 0 SLICEs Net jtaghub_inst.er1_shift_reg8: 23 loads, 23 SLICEs Net ip_enable[0]: 37 loads, 37 SLICEs Net jtaghub_inst.JUPDATE: 13 loads, 13 SLICEs Net secured_signal_306: 11 loads, 11 SLICEs Net secured_signal_310: 5 loads, 5 SLICEs Net secured_signal_349: 5 loads, 5 SLICEs Net secured_signal_371: 12 loads, 12 SLICEs Net secured_signal_374: 1 loads, 1 SLICEs Net secured_signal_375: 1 loads, 1 SLICEs Net secured_signal_379: 2 loads, 2 SLICEs Net secured_signal_416: 37 loads, 37 SLICEs Net secured_signal_419: 9 loads, 9 SLICEs Net secured_signal_423: 5 loads, 5 SLICEs Net secured_signal_437: 9 loads, 9 SLICEs Net secured_signal_470: 11 loads, 9 SLICEs Net secured_signal_501: 5 loads, 5 SLICEs Net secured_signal_505: 9 loads, 9 SLICEs Net secured_signal_763: 20 loads, 20 SLICEs Net secured_signal_819: 2 loads, 2 SLICEs Net secured_signal_820: 1 loads, 1 SLICEs Net secured_signal_826: 43 loads, 43 SLICEs Net secured_signal_898: 16 loads, 16 SLICEs Net secured_signal_912: 1 loads, 1 SLICEs Net secured_signal_914: 4 loads, 4 SLICEs Net secured_signal_1003: 16 loads, 16 SLICEs Net secured_signal_1081: 1 loads, 1 SLICEs Net secured_signal_1096: 2 loads, 2 SLICEs Net secured_signal_1196: 2 loads, 2 SLICEs Net secured_signal_1205: 3 loads, 3 SLICEs Net secured_signal_1208: 1 loads, 1 SLICEs Net secured_signal_1209: 1 loads, 1 SLICEs Net secured_signal_1225: 9 loads, 9 SLICEs Net secured_signal_1235: 1 loads, 1 SLICEs Net secured_signal_1237: 1 loads, 1 SLICEs Net secured_signal_1239: 1 loads, 1 SLICEs Net secured_signal_1245: 1 loads, 1 SLICEs Net secured_signal_1255: 16 loads, 16 SLICEs Net secured_signal_1258: 2 loads, 2 SLICEs Net secured_signal_1269: 2 loads, 2 SLICEs Net secured_signal_1287: 1 loads, 0 SLICEs Net secured_signal_1289: 1 loads, 1 SLICEs Net secured_signal_1344: 7 loads, 7 SLICEs Net secured_signal_1345: 7 loads, 7 SLICEs Net secured_signal_1385: 3 loads, 3 SLICEs Pin SW[2]: 1 loads, 0 SLICEs (Net: SW_c[2]) Number of LSRs: 5 Net VCC: 11 loads, 0 SLICEs Net jrstn: 247 loads, 246 SLICEs Net secured_signal_1191: 1 loads, 1 SLICEs Net i_PLL1.lscc_pll_inst.pll_lock: 6 loads, 6 SLICEs Net i_PLL1.lscc_pll_inst.SW_c_i[0]: 1 loads, 0 SLICEs Top 10 highest fanout non-clock nets: Net jrstn: 248 loads Net VCC: 89 loads Net Lab1_reveal_coretop_instance.lab1_la0_inst_0.jshift_d1: 72 loads Net ip_enable[0]: 53 loads Net Lab1_reveal_coretop_instance.lab1_la0_inst_0.addr[0]: 49 loads Net jshift: 46 loads Net secured_signal_826: 43 loads Net Lab1_reveal_coretop_instance.lab1_la0_inst_0.tr_bit_0: 40 loads Net Lab1_reveal_coretop_instance.lab1_la0_inst_0.addr[1]: 39 loads Net secured_signal_416: 37 loads Number of warnings: 2 Number of errors: 0 Number of errors: 0 Design Errors/Warnings WARNING - map: Top module port 'SW[3]' does not connect to anything. WARNING - map: Top module port 'SW[3]' does not connect to anything. IO (PIO) Attributes +---------------------+-----------+-----------+-------+-------+-----------+ | IO Name | Direction | Levelmode | IO | IO | Special | | | | IO_TYPE | REG | DDR | IO Buffer | +---------------------+-----------+-----------+-------+-------+-----------+ | TDI | INPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | TCK | INPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | TMS | INPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | TDO | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | SEG_OUT[7] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | SEG_OUT[6] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | SEG_OUT[5] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | SEG_OUT[4] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | SEG_OUT[3] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | SEG_OUT[2] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | SEG_OUT[1] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | SEG_OUT[0] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | LED_OUT[7] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | LED_OUT[6] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | LED_OUT[5] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | LED_OUT[4] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | LED_OUT[3] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | LED_OUT[2] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | LED_OUT[1] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | LED_OUT[0] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | MON[3] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | MON[2] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | MON[1] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | MON[0] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | ROM_OUT[17] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | ROM_OUT[16] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | ROM_OUT[15] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | ROM_OUT[14] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | ROM_OUT[13] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | ROM_OUT[12] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | ROM_OUT[11] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | ROM_OUT[10] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | ROM_OUT[9] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | ROM_OUT[8] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | ROM_OUT[7] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | ROM_OUT[6] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | ROM_OUT[5] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | ROM_OUT[4] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | ROM_OUT[3] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | ROM_OUT[2] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | ROM_OUT[1] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | ROM_OUT[0] | OUTPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | SW[2] | INPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | SW[1] | INPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ | SW[0] | INPUT | | | | | +---------------------+-----------+-----------+-------+-------+-----------+ Removed logic Block jtaghub_inst/IP_ENABLE_reg[17].ff_inst undriven or does not drive anything - clipped. Block jtaghub_inst/IP_ENABLE_reg[16].ff_inst undriven or does not drive anything - clipped. Block jtaghub_inst/IP_ENABLE_reg[15].ff_inst undriven or does not drive anything - clipped. Block jtaghub_inst/IP_ENABLE_reg[14].ff_inst undriven or does not drive anything - clipped. Block jtaghub_inst/IP_ENABLE_reg[13].ff_inst undriven or does not drive anything - clipped. Block jtaghub_inst/IP_ENABLE_reg[12].ff_inst undriven or does not drive anything - clipped. Block jtaghub_inst/IP_ENABLE_fast_reg[11].ff_inst undriven or does not drive anything - clipped. Block jtaghub_inst/IP_ENABLE_reg[11].ff_inst undriven or does not drive anything - clipped. Block jtaghub_inst/IP_ENABLE_fast_reg[3].ff_inst undriven or does not drive anything - clipped. Block jtaghub_inst/jtdo2_int_m15_N_2L1_cZ undriven or does not drive anything - clipped. Block jtaghub_inst/GSR_INST.GSR_inst undriven or does not drive anything - clipped. Block VCC_cZ was optimized away. Block jtaghub_inst/jtdo2_int_m15_cZ was optimized away. Block i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL_RNI12ID was optimized away. Block jtaghub_inst/IP_ENABLE_0_.CN was optimized away. Block jtaghub_inst/OBZ_inst_RNO was optimized away. Block jtaghub_inst/jtagg_u_RNI1T52 was optimized away. Block jtaghub_inst/jtdo2_int_m11_cZ was optimized away. Block jtaghub_inst/jtdo2_int_m11_1_cZ was optimized away. Block jtaghub_inst/jtdo2_int_m8_1_cZ was optimized away. Block jtaghub_inst/jtdo2_int_m11_1_0_cZ was optimized away. Block jtaghub_inst/jtdo2_int_m2_cZ was optimized away. Block jtaghub_inst/jtdo2_int_m2_1_cZ was optimized away. Block jtaghub_inst/jtagg_u_RNO_2_cZ was optimized away. Block jtaghub_inst/jtdo2_int_m5_cZ was optimized away. Block jtaghub_inst/jtdo2_int_m5_1_cZ was optimized away. Block jtaghub_inst/jtdo2_int_m2_bm_cZ was optimized away. Block jtaghub_inst/jtdo2_int_m5_bm_cZ was optimized away. PLL/DLL Summary --------------- PLL 1: Pin/Node Value PLL Instance Name: i_PLL1/lscc_pll_inst/gen_no_refc lk_mon.u_PLL.PLL_inst Input Reference Clock: NODE MON_c[0] Output Clock(P): NODE clk48m[0] Output Clock(S): NONE Output Clock(S2): NONE Output Clock(S3): NONE Output Clock(S4): NONE Output Clock(S5): NONE Feedback Signal: NODE clk48m[0] Reset Signal: NODE i_PLL1.lscc_pll_inst.SW_c_i[0] Standby Signal: NODE GND PLL LOCK signal: NODE i_PLL1.lscc_pll_inst.pll_lock PLL Internal LOCK Signal: NONE A Divider: 30 B Divider: 7 C Divider: 7 D Divider: 7 E Divider: 7 F Divider: 7 A Post Divider Shift: 30 B Post Divider Shift: 7 C Post Divider Shift: 7 D Post Divider Shift: 7 E Post Divider Shift: 7 F Post Divider Shift: 7 A Section VCO Phase Shift: 0 B Section VCO Phase Shift: 0 C Section VCO Phase Shift: 0 D Section VCO Phase Shift: 0 E Section VCO Phase Shift: 0 F Section VCO Phase Shift: 0 CLKOP Trim Setting: 0000 CLKOS Trim Setting: 0000 CLKOS2 Trim Setting: 0000 CLKOS3 Trim Setting: 0000 CLKOS4 Trim Setting: 0000 CLKOS5 Trim Setting: 0000 OSC Summary ----------- OSC 1: Pin/Node Value OSC Instance Name: i_OSCA.OSCA_inst Enable High Frequency SDSC: NODE GND High Frequency Output: PIN,NODE MON_c[0] Low Frequency Output: NONE SDC Output: NONE High Frequency DIV: 19 ASIC Components --------------- Instance Name: jtaghub_inst/jtagg_u Type: CONFIG_JTAG_CORE Instance Name: secured_comp_373 Type: EBR_CORE Instance Name: secured_comp_374 Type: EBR_CORE Instance Name: secured_comp_1069 Type: EBR_CORE Instance Name: i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst Type: PLL_CORE Instance Name: i_RAM_DP1/lscc_ram_dp_inst/mem_main/NON_MIX.ADDR_ROUTE[0].DATA_RO UTE[0].mem_init.u_mem0/LIFCL_MEM.pdp16k.PDP16K_MODE_inst Type: EBR_CORE Instance Name: i_MULT/lscc_multiplier_inst/genblk1.u_lscc_multiplier_dsp/Z\U_PIP ELINES_GT_0.pp_pipe_[0]_0_5_0_.DSP_GUT[17:0].PREADD9_L0 Type: PREADD9_CORE Instance Name: i_MULT/lscc_multiplier_inst/genblk1.u_lscc_multiplier_dsp/Z\U_PIP ELINES_GT_0.pp_pipe_[0]_0_5_0_.DSP_GUT[17:0].MULT9_L0 Type: MULT9_CORE Instance Name: i_MULT/lscc_multiplier_inst/genblk1.u_lscc_multiplier_dsp/Z\U_PIP ELINES_GT_0.pp_pipe_[0]_0_5_0_.DSP_GUT[17:0].REG18_L0_0 Type: REG18_CORE Instance Name: i_OSCA.OSCA_inst Type: OSC_CORE UFM Usage of +------------+-------------------+--------+ | | Start Address | Size | +------------+-------------------+--------+ +------------+-------------------+--------+ GSR Usage --------- GSR Component: The Global Set Reset (GSR) resource has been used to implement a global reset of the design. The reset signal used for GSR control is 'Lab1_reveal_coretop_instance.lab1_la0_inst_0.reset_rvl_n'. GSR Property: The design components with GSR property set to ENABLED will respond to global set reset while the components with GSR property set to DISABLED will not. Components with disabled GSR Property ------------------------------------- These components have the GSR property set to DISABLED. The components will not respond to the reset signal 'Lab1_reveal_coretop_instance.lab1_la0_inst_0.reset_rvl_n' via the GSR component. Type and number of components of the type: Register = 325 Type and instance name of component: Register : jtaghub_inst.rom_rd_addr_reg[0].ff_inst Register : jtaghub_inst.rom_rd_addr_reg[1].ff_inst Register : jtaghub_inst.rom_rd_addr_reg[2].ff_inst Register : jtaghub_inst.rom_rd_addr_reg[3].ff_inst Register : jtaghub_inst.rom_rd_addr_reg[4].ff_inst Register : jtaghub_inst.rom_rd_addr_reg[5].ff_inst Register : jtaghub_inst.jshift_d1.ff_inst Register : jtaghub_inst.jce1_d1_reg.ff_inst Register : jtaghub_inst.id_enable_reg.ff_inst Register : jtaghub_inst.er1_shift_reg_reg[1].ff_inst Register : jtaghub_inst.er1_shift_reg_reg[2].ff_inst Register : jtaghub_inst.er1_shift_reg_reg[3].ff_inst Register : jtaghub_inst.er1_shift_reg_reg[4].ff_inst Register : jtaghub_inst.er1_shift_reg_reg[5].ff_inst Register : jtaghub_inst.er1_shift_reg_reg[6].ff_inst Register : jtaghub_inst.er1_shift_reg_reg[7].ff_inst Register : jtaghub_inst.er1_shift_reg_reg[8].ff_inst Register : jtaghub_inst.er1_shift_reg_reg[9].ff_inst Register : jtaghub_inst.er1_shift_reg_reg[10].ff_inst Register : jtaghub_inst.er1_shift_reg_reg[11].ff_inst Register : jtaghub_inst.er1_shift_reg_reg[12].ff_inst Register : jtaghub_inst.er1_shift_reg_reg[13].ff_inst Register : jtaghub_inst.er1_shift_reg_reg[14].ff_inst Register : jtaghub_inst.er1_shift_reg_reg[15].ff_inst Register : jtaghub_inst.er1_shift_reg_reg[16].ff_inst Register : jtaghub_inst.er1_shift_reg_reg[17].ff_inst Register : jtaghub_inst.er1_shift_reg_reg[18].ff_inst Register : jtaghub_inst.er1_shift_reg_reg[19].ff_inst Register : jtaghub_inst.er1_shift_reg_reg[20].ff_inst Register : jtaghub_inst.er1_shift_reg_reg[21].ff_inst Register : jtaghub_inst.er1_shift_reg_reg[22].ff_inst Register : jtaghub_inst.er1_shift_reg_reg[23].ff_inst Register : jtaghub_inst.bit_count_reg[0].ff_inst Register : jtaghub_inst.bit_count_reg[1].ff_inst Register : jtaghub_inst.bit_count_reg[2].ff_inst Register : jtaghub_inst.bit_count_reg[3].ff_inst Register : jtaghub_inst.bit_count_reg[4].ff_inst Register : jtaghub_inst.IP_ENABLE_reg[1].ff_inst Register : jtaghub_inst.IP_ENABLE_reg[2].ff_inst Register : jtaghub_inst.IP_ENABLE_reg[3].ff_inst Register : jtaghub_inst.IP_ENABLE_reg[4].ff_inst Register : jtaghub_inst.IP_ENABLE_reg[5].ff_inst Register : jtaghub_inst.IP_ENABLE_reg[6].ff_inst Register : jtaghub_inst.IP_ENABLE_reg[7].ff_inst Register : jtaghub_inst.IP_ENABLE_fast_reg[8].ff_inst Register : jtaghub_inst.IP_ENABLE_reg[8].ff_inst Register : jtaghub_inst.IP_ENABLE_reg[9].ff_inst Register : jtaghub_inst.IP_ENABLE_reg[10].ff_inst Register : secured_comp_389 Register : secured_comp_390 Register : secured_comp_391 Register : secured_comp_392 Register : secured_comp_393 Register : secured_comp_394 Register : secured_comp_395 Register : secured_comp_396 Register : secured_comp_397 Register : secured_comp_398 Register : secured_comp_399 Register : secured_comp_400 Register : secured_comp_401 Register : secured_comp_402 Register : secured_comp_403 Register : secured_comp_404 Register : secured_comp_405 Register : secured_comp_406 Register : secured_comp_407 Register : secured_comp_408 Register : secured_comp_409 Register : secured_comp_410 Register : secured_comp_411 Register : secured_comp_412 Register : secured_comp_413 Register : secured_comp_414 Register : secured_comp_415 Register : secured_comp_416 Register : secured_comp_417 Register : secured_comp_418 Register : secured_comp_419 Register : secured_comp_420 Register : secured_comp_421 Register : secured_comp_422 Register : secured_comp_423 Register : secured_comp_424 Register : secured_comp_425 Register : secured_comp_472 Register : secured_comp_473 Register : secured_comp_474 Register : secured_comp_475 Register : secured_comp_476 Register : secured_comp_477 Register : secured_comp_478 Register : secured_comp_479 Register : secured_comp_480 Register : secured_comp_481 Register : secured_comp_482 Register : secured_comp_483 Register : secured_comp_814 Register : secured_comp_815 Register : secured_comp_816 Register : secured_comp_817 Register : secured_comp_818 Register : secured_comp_819 Register : secured_comp_820 Register : secured_comp_821 Register : secured_comp_822 Register : secured_comp_823 Register : secured_comp_824 Register : secured_comp_825 Register : secured_comp_826 Register : secured_comp_827 Register : secured_comp_828 Register : secured_comp_829 Register : secured_comp_830 Register : secured_comp_831 Register : secured_comp_832 Register : secured_comp_833 Register : secured_comp_834 Register : secured_comp_835 Register : secured_comp_836 Register : secured_comp_837 Register : secured_comp_838 Register : secured_comp_839 Register : secured_comp_840 Register : secured_comp_841 Register : secured_comp_842 Register : secured_comp_843 Register : secured_comp_844 Register : secured_comp_845 Register : secured_comp_846 Register : secured_comp_847 Register : secured_comp_848 Register : secured_comp_849 Register : secured_comp_850 Register : secured_comp_851 Register : secured_comp_852 Register : secured_comp_853 Register : secured_comp_854 Register : secured_comp_855 Register : secured_comp_856 Register : secured_comp_857 Register : secured_comp_858 Register : secured_comp_859 Register : secured_comp_860 Register : secured_comp_861 Register : secured_comp_862 Register : secured_comp_863 Register : secured_comp_864 Register : secured_comp_865 Register : secured_comp_866 Register : secured_comp_867 Register : secured_comp_868 Register : secured_comp_869 Register : secured_comp_870 Register : secured_comp_871 Register : secured_comp_872 Register : secured_comp_873 Register : secured_comp_874 Register : secured_comp_875 Register : secured_comp_876 Register : secured_comp_877 Register : secured_comp_878 Register : secured_comp_879 Register : secured_comp_880 Register : secured_comp_881 Register : secured_comp_882 Register : secured_comp_883 Register : secured_comp_884 Register : secured_comp_885 Register : secured_comp_886 Register : secured_comp_887 Register : secured_comp_888 Register : secured_comp_889 Register : secured_comp_890 Register : secured_comp_891 Register : secured_comp_892 Register : secured_comp_893 Register : secured_comp_894 Register : secured_comp_895 Register : secured_comp_896 Register : secured_comp_897 Register : secured_comp_898 Register : secured_comp_899 Register : secured_comp_900 Register : secured_comp_901 Register : secured_comp_902 Register : secured_comp_903 Register : secured_comp_904 Register : secured_comp_905 Register : secured_comp_906 Register : secured_comp_907 Register : secured_comp_908 Register : secured_comp_909 Register : secured_comp_910 Register : secured_comp_911 Register : secured_comp_912 Register : secured_comp_913 Register : secured_comp_914 Register : secured_comp_915 Register : secured_comp_916 Register : secured_comp_917 Register : secured_comp_918 Register : secured_comp_919 Register : secured_comp_920 Register : secured_comp_921 Register : secured_comp_922 Register : secured_comp_923 Register : secured_comp_924 Register : secured_comp_925 Register : secured_comp_926 Register : secured_comp_927 Register : secured_comp_928 Register : secured_comp_929 Register : secured_comp_930 Register : secured_comp_931 Register : secured_comp_932 Register : secured_comp_933 Register : secured_comp_934 Register : secured_comp_935 Register : secured_comp_940 Register : secured_comp_941 Register : secured_comp_942 Register : secured_comp_943 Register : secured_comp_944 Register : secured_comp_945 Register : secured_comp_946 Register : secured_comp_947 Register : secured_comp_948 Register : secured_comp_949 Register : secured_comp_950 Register : secured_comp_951 Register : secured_comp_956 Register : secured_comp_957 Register : secured_comp_958 Register : secured_comp_959 Register : secured_comp_960 Register : secured_comp_961 Register : secured_comp_962 Register : secured_comp_963 Register : secured_comp_964 Register : secured_comp_965 Register : secured_comp_966 Register : secured_comp_967 Register : secured_comp_968 Register : secured_comp_1070 Register : secured_comp_1071 Register : secured_comp_1072 Register : secured_comp_1073 Register : secured_comp_1074 Register : secured_comp_1078 Register : secured_comp_1079 Register : secured_comp_1080 Register : secured_comp_1081 Register : secured_comp_1082 Register : secured_comp_1083 Register : secured_comp_1084 Register : secured_comp_1085 Register : secured_comp_1086 Register : secured_comp_1087 Register : secured_comp_1088 Register : secured_comp_1089 Register : secured_comp_1090 Register : secured_comp_1091 Register : secured_comp_1092 Register : secured_comp_1093 Register : secured_comp_1094 Register : secured_comp_1095 Register : secured_comp_1096 Register : secured_comp_1097 Register : secured_comp_1098 Register : secured_comp_1099 Register : secured_comp_1100 Register : secured_comp_1101 Register : secured_comp_1102 Register : secured_comp_1103 Register : secured_comp_1104 Register : secured_comp_1105 Register : secured_comp_1106 Register : secured_comp_1107 Register : secured_comp_1108 Register : secured_comp_1109 Register : secured_comp_1119 Register : i_RAM_DP1.lscc_ram_dp_inst.mem_main.NON_MIX.ADDR_ROUTE[0].DATA_ROU TE[0].genblk3.f_rd_en_r.ff_inst Register : i_MULT.lscc_multiplier_inst.genblk1.u_lscc_multiplier_dsp.result_o _mod[0].ff_inst Register : i_MULT.lscc_multiplier_inst.genblk1.u_lscc_multiplier_dsp.result_o _mod[1].ff_inst Register : i_MULT.lscc_multiplier_inst.genblk1.u_lscc_multiplier_dsp.result_o _mod[2].ff_inst Register : i_MULT.lscc_multiplier_inst.genblk1.u_lscc_multiplier_dsp.result_o _mod[3].ff_inst Register : i_MULT.lscc_multiplier_inst.genblk1.u_lscc_multiplier_dsp.result_o _mod[4].ff_inst Register : i_MULT.lscc_multiplier_inst.genblk1.u_lscc_multiplier_dsp.result_o _mod[5].ff_inst Register : led_cont_reg[0].ff_inst Register : led_cont_reg[1].ff_inst Register : led_cont_reg[2].ff_inst Register : led_cont_reg[3].ff_inst Register : led_cont_reg[4].ff_inst Register : led_cont_reg[5].ff_inst Register : led_cont_reg[6].ff_inst Register : led_cont_reg[7].ff_inst Register : led_cont_reg[8].ff_inst Register : led_cont_reg[9].ff_inst Register : led_cont_reg[10].ff_inst Register : led_cont_reg[11].ff_inst Register : led_cont_reg[12].ff_inst Register : led_cont_reg[13].ff_inst Register : led_cont_reg[14].ff_inst Register : led_cont_reg[15].ff_inst Register : led_cont_reg[16].ff_inst Register : led_cont_reg[17].ff_inst Register : led_cont_reg[18].ff_inst Register : led_cont_reg[19].ff_inst Register : led_cont_reg[20].ff_inst Register : led_cont_reg[21].ff_inst Register : led_cont_reg[22].ff_inst Register : led_cont_reg[23].ff_inst Register : led_cont_reg[24].ff_inst Register : led_cont_reg[25].ff_inst Register : freq_cont[0].ff_inst Register : freq_cont[1].ff_inst Register : freq_cont[2].ff_inst Register : freq_cont_reg[3].ff_inst Register : freq_cont_reg[4].ff_inst Register : freq_cont_reg[5].ff_inst Register : freq_cont_reg[6].ff_inst Register : freq_cont_reg[7].ff_inst Register : freq_cont_reg[8].ff_inst Register : freq_cont_reg[9].ff_inst Components with synchronous local reset also reset by asynchronous GSR ---------------------------------------------------------------------- These components have the GSR property set to ENABLED and the local reset is synchronous. The components will respond to the synchronous local reset and to the unrelated asynchronous reset signal 'Lab1_reveal_coretop_instance.lab1_la0_inst_0.reset_rvl_n' via the GSR component. Type and number of components of the type: Register = 230 MULT9_CORE = 1, REG18_CORE = 1 , EBR_CORE = 4 , PREADD9_CORE = 1 Type and instance name of component: Register : secured_comp_336 Register : secured_comp_337 Register : secured_comp_338 Register : secured_comp_339 Register : secured_comp_340 Register : secured_comp_341 Register : secured_comp_342 Register : secured_comp_343 Register : secured_comp_344 Register : secured_comp_345 Register : secured_comp_346 Register : secured_comp_347 Register : secured_comp_348 Register : secured_comp_349 Register : secured_comp_350 Register : secured_comp_351 Register : secured_comp_352 Register : secured_comp_353 Register : secured_comp_354 Register : secured_comp_355 Register : secured_comp_356 Register : secured_comp_357 Register : secured_comp_358 Register : secured_comp_359 Register : secured_comp_360 Register : secured_comp_361 Register : secured_comp_362 Register : secured_comp_363 Register : secured_comp_364 Register : secured_comp_365 Register : secured_comp_366 Register : secured_comp_367 Register : secured_comp_368 Register : secured_comp_369 Register : secured_comp_370 Register : secured_comp_371 Register : secured_comp_372 Register : secured_comp_375 Register : secured_comp_376 Register : secured_comp_377 Register : secured_comp_378 Register : secured_comp_379 Register : secured_comp_380 Register : secured_comp_381 Register : secured_comp_382 Register : secured_comp_383 Register : secured_comp_384 Register : secured_comp_385 Register : secured_comp_386 Register : secured_comp_387 Register : secured_comp_388 Register : secured_comp_426 Register : secured_comp_427 Register : secured_comp_428 Register : secured_comp_429 Register : secured_comp_430 Register : secured_comp_431 Register : secured_comp_432 Register : secured_comp_433 Register : secured_comp_434 Register : secured_comp_435 Register : secured_comp_436 Register : secured_comp_437 Register : secured_comp_438 Register : secured_comp_439 Register : secured_comp_440 Register : secured_comp_441 Register : secured_comp_442 Register : secured_comp_443 Register : secured_comp_444 Register : secured_comp_445 Register : secured_comp_446 Register : secured_comp_447 Register : secured_comp_448 Register : secured_comp_449 Register : secured_comp_450 Register : secured_comp_451 Register : secured_comp_452 Register : secured_comp_453 Register : secured_comp_454 Register : secured_comp_455 Register : secured_comp_456 Register : secured_comp_457 Register : secured_comp_458 Register : secured_comp_459 Register : secured_comp_460 Register : secured_comp_461 Register : secured_comp_462 Register : secured_comp_463 Register : secured_comp_464 Register : secured_comp_465 Register : secured_comp_466 Register : secured_comp_467 Register : secured_comp_468 Register : secured_comp_469 Register : secured_comp_470 Register : secured_comp_471 Register : secured_comp_484 Register : secured_comp_485 Register : secured_comp_486 Register : secured_comp_487 Register : secured_comp_488 Register : secured_comp_489 Register : secured_comp_490 Register : secured_comp_491 Register : secured_comp_492 Register : secured_comp_493 Register : secured_comp_494 Register : secured_comp_495 Register : secured_comp_496 Register : secured_comp_497 Register : secured_comp_498 Register : secured_comp_499 Register : secured_comp_500 Register : secured_comp_501 Register : secured_comp_502 Register : secured_comp_503 Register : secured_comp_504 Register : secured_comp_505 Register : secured_comp_506 Register : secured_comp_507 Register : secured_comp_508 Register : secured_comp_509 Register : secured_comp_510 Register : secured_comp_511 Register : secured_comp_512 Register : secured_comp_513 Register : secured_comp_514 Register : secured_comp_515 Register : secured_comp_516 Register : secured_comp_517 Register : secured_comp_518 Register : secured_comp_519 Register : secured_comp_520 Register : secured_comp_521 Register : secured_comp_522 Register : secured_comp_523 Register : secured_comp_524 Register : secured_comp_525 Register : secured_comp_526 Register : secured_comp_527 Register : secured_comp_528 Register : secured_comp_529 Register : secured_comp_530 Register : secured_comp_531 Register : secured_comp_532 Register : secured_comp_533 Register : secured_comp_534 Register : secured_comp_535 Register : secured_comp_536 Register : secured_comp_537 Register : secured_comp_538 Register : secured_comp_539 Register : secured_comp_540 Register : secured_comp_541 Register : secured_comp_542 Register : secured_comp_543 Register : secured_comp_544 Register : secured_comp_545 Register : secured_comp_546 Register : secured_comp_547 Register : secured_comp_548 Register : secured_comp_549 Register : secured_comp_550 Register : secured_comp_551 Register : secured_comp_552 Register : secured_comp_936 Register : secured_comp_937 Register : secured_comp_938 Register : secured_comp_939 Register : secured_comp_952 Register : secured_comp_953 Register : secured_comp_954 Register : secured_comp_955 Register : secured_comp_998 Register : secured_comp_999 Register : secured_comp_1000 Register : secured_comp_1001 Register : secured_comp_1002 Register : secured_comp_1003 Register : secured_comp_1004 Register : secured_comp_1005 Register : secured_comp_1006 Register : secured_comp_1007 Register : secured_comp_1008 Register : secured_comp_1009 Register : secured_comp_1075 Register : secured_comp_1076 Register : secured_comp_1077 Register : secured_comp_1110 Register : secured_comp_1111 Register : secured_comp_1112 Register : secured_comp_1113 Register : secured_comp_1114 Register : secured_comp_1115 Register : secured_comp_1116 Register : secured_comp_1117 Register : secured_comp_1118 Register : secured_comp_1166 Register : secured_comp_1167 Register : secured_comp_1168 Register : secured_comp_1169 Register : secured_comp_1170 Register : secured_comp_1171 Register : secured_comp_1172 Register : secured_comp_1173 Register : secured_comp_1174 Register : secured_comp_1175 Register : secured_comp_1176 Register : secured_comp_1177 Register : secured_comp_1178 Register : secured_comp_1179 Register : secured_comp_1180 Register : secured_comp_1181 Register : secured_comp_1182 Register : secured_comp_1183 Register : secured_comp_1184 Register : secured_comp_1185 Register : secured_comp_1186 Register : secured_comp_1187 Register : secured_comp_1188 Register : secured_comp_1189 Register : secured_comp_1190 Register : secured_comp_1191 Register : secured_comp_1192 Register : secured_comp_1193 Register : secured_comp_1194 Register : secured_comp_1195 Register : secured_comp_1196 Register : secured_comp_1197 EBR_CORE : secured_comp_373 EBR_CORE : secured_comp_374 EBR_CORE : secured_comp_1069 EBR_CORE : i_RAM_DP1.lscc_ram_dp_inst.mem_main.NON_MIX.ADDR_ROUTE[0].DATA_ROU TE[0].mem_init.u_mem0.LIFCL_MEM.pdp16k.PDP16K_MODE_inst PREADD9_CORE : i_MULT.lscc_multiplier_inst.genblk1.u_lscc_multiplier_dsp.Z\U_ PIPELINES_GT_0.pp_pipe_[0]_0_5_0_.DSP_GUT[17:0].PREADD9_L0 MULT9_CORE : i_MULT.lscc_multiplier_inst.genblk1.u_lscc_multiplier_dsp.Z\U_PI PELINES_GT_0.pp_pipe_[0]_0_5_0_.DSP_GUT[17:0].MULT9_L0 REG18_CORE : i_MULT.lscc_multiplier_inst.genblk1.u_lscc_multiplier_dsp.Z\U_PI PELINES_GT_0.pp_pipe_[0]_0_5_0_.DSP_GUT[17:0].REG18_L0_0 Block RAM components with enabled GSR ------------------------------- These Block RAM components have the GSR property set to ENABLED. The components will respond to the asynchronous reset signal 'Lab1_reveal_coretop_instance.lab1_la0_inst_0.reset_rvl_n' via the GSR component. Type and number of components of the type: EBR_CORE = 4 Type and instance name of component: EBR_CORE : secured_comp_373 EBR_CORE : secured_comp_374 EBR_CORE : secured_comp_1069 EBR_CORE : i_RAM_DP1.lscc_ram_dp_inst.mem_main.NON_MIX.ADDR_ROUTE[0].DATA_ROU TE[0].mem_init.u_mem0.LIFCL_MEM.pdp16k.PDP16K_MODE_inst Run Time and Memory Usage ------------------------- Total CPU Time: 4 secs Total REAL Time: 5 secs Peak Memory Usage: 267 MB Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2022 Lattice Semiconductor Corporation, All rights reserved.