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Tool: Synplify Pro (R)
Build: S-2021.09LR-2
Install: C:\lscc\radiant\3.2\synpbase
OS: Windows 10 or later
Hostname: HD12801B

Implementation : impl_1

# Written on Fri Nov 11 17:05:41 2022

##### DESIGN INFO #######################################################

Top View:                "Lab1"
Constraint File(s):      "C:\Users\12801\Downloads\Radiant_Seminar_ond\Sample\Lab1\impl_1\Lab1_impl_1_cpe.ldc"
                         "C:\lscc\radiant\3.2\data\reveal\src\ertl\reveal_constraint.sdc"




##### SUMMARY ############################################################

Found 1 issues in 1 out of 3 constraints


##### DETAILS ############################################################



Clock Relationships
*******************

Starting                     Ending                       |     rise to rise     |     fall to fall     |     rise to fall     |     fall to rise                     
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                       System                       |     5.000            |     No paths         |     No paths         |     No paths                         
System                       clk48m                       |     20.833           |     No paths         |     No paths         |     No paths                         
System                       Lab1|jtck_inferred_clock     |     No paths         |     No paths         |     5.000            |     No paths                         
clk48m                       System                       |     20.833           |     No paths         |     No paths         |     No paths                         
clk48m                       clk48m                       |     20.833           |     No paths         |     No paths         |     No paths                         
clk48m                       Lab1|jtck_inferred_clock     |     No paths         |     No paths         |     Diff grp         |     No paths                         
Lab1|jtck_inferred_clock     System                       |     No paths         |     No paths         |     No paths         |     5.000                            
Lab1|jtck_inferred_clock     clk48m                       |     No paths         |     No paths         |     No paths         |     Diff grp                         
Lab1|jtck_inferred_clock     Lab1|jtck_inferred_clock     |     No paths         |     5.000            |     No paths         |     No paths                         
=====================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.


Unconstrained Start/End Points
******************************

p:LED_OUT[0]
p:LED_OUT[1]
p:LED_OUT[2]
p:LED_OUT[3]
p:LED_OUT[4]
p:LED_OUT[5]
p:LED_OUT[6]
p:LED_OUT[7]
p:MON[0]
p:MON[1]
p:MON[2]
p:MON[3]
p:ROM_OUT[0]
p:ROM_OUT[1]
p:ROM_OUT[2]
p:ROM_OUT[3]
p:ROM_OUT[4]
p:ROM_OUT[5]
p:ROM_OUT[6]
p:ROM_OUT[7]
p:ROM_OUT[8]
p:ROM_OUT[9]
p:ROM_OUT[10]
p:ROM_OUT[11]
p:ROM_OUT[12]
p:ROM_OUT[13]
p:ROM_OUT[14]
p:ROM_OUT[15]
p:ROM_OUT[16]
p:ROM_OUT[17]
p:SEG_OUT[0]
p:SEG_OUT[1]
p:SEG_OUT[2]
p:SEG_OUT[3]
p:SEG_OUT[4]
p:SEG_OUT[5]
p:SEG_OUT[6]
p:SEG_OUT[7]
p:SW[0]
p:SW[1]
p:SW[2]
p:SW[3]
p:TDI
p:TDO
p:TMS


Inapplicable constraints
************************

(none)


Applicable constraints with issues
**********************************

create_clock -name clk48m -period 20.8333333333333 [get_nets clk48m]
	@W::"c:/users/12801/downloads/radiant_seminar_ond/sample/lab1/impl_1/lab1_impl_1_cpe.ldc":3:0:3:0|Source for clock clk48m should be moved to net i_PLL1.lscc_pll_inst.clkop_o connected to driving cell pin i_PLL1.lscc_pll_inst.\\gen_no_refclk_mon\.u_PLL.CLKOP

Constraints with matching wildcard expressions
**********************************************

(none)


Library Report
**************


# End of Constraint Checker Report