Timing Report
Lattice Timing Report - Setup and Hold, Version Radiant Software (64-bit) 3.2.1.217.3
Fri Nov 11 17:06:31 2022
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2022 Lattice Semiconductor Corporation, All rights reserved.
Command line: timing -sethld -v 10 -u 10 -endpoints 10 -nperend 1 -sp 8_High-Performance_1.0V -hsp m -pwrprd -html -rpt Lab1_impl_1.twr Lab1_impl_1.udb -gui
-------------------------------------------
Design: Lab1
Family: LFMXO5
Device: LFMXO5-25
Package: BBG400
Performance: 8_High-Performance_1.0V
Package Status: Preliminary Version 7
Performance Hardware Data Status : Preliminary Version 1.6
-------------------------------------------
=====================================================================
Table of Contents
=====================================================================
1 DESIGN CHECKING
1.1 SDC Constraints
1.2 Combinational Loop
1.3 Error/Warning Messages
2 CLOCK SUMMARY
2.1 Clock MON_c[0]
2.2 Clock rvltck
2.3 Clock clk48m[0]
3 TIMING ANALYSIS SUMMARY
3.1 Overall (Setup and Hold)
3.1.1 Constraint Coverage
3.1.2 Timing Errors
3.1.3 Total Timing Score
3.2 Setup Summary Report
3.3 Hold Summary Report
3.4 Unconstrained Report
3.4.1 Unconstrained Start/End Points
3.4.2 Start/End Points Without Timing Constraints
4 DETAILED REPORT
4.1 Setup Detailed Report
4.2 Hold Detailed Report
=====================================================================
End of Table of Contents
=====================================================================
1 DESIGN CHECKING
1.1 SDC Constraints
create_clock -name {MON_c[0]} -period 44.4444 [get_pins {i_OSCA.OSCA_inst/HFCLKOUT }]
create_clock -name {rvltck} -period 33.33 -waveform {0.000 16.665} [get_ports TCK]
create_clock -name {clk48m[0]} -period 20.8333333333333 [get_nets {clk48m[0]}]
set_false_path -from [get_clocks {clk48m[0]}] -to [get_clocks rvltck]
set_false_path -from [get_clocks rvltck] -to [get_clocks {clk48m[0]}]
Operating conditions:
--------------------
Temperature: 85C
1.2 Combinational Loop
1.3 Error/Warning Messages
WARNING - The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
2 CLOCK SUMMARY
2.1 Clock "MON_c[0]"
create_clock -name {MON_c[0]} -period 44.4444 [get_pins {i_OSCA.OSCA_inst/HFCLKOUT }]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock MON_c[0] | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From MON_c[0] | Target | 44.444 ns | 22.500 MHz
| Actual (all paths) | 5.000 ns | 200.000 MHz
MON_pad[0].bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock MON_c[0] | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From rvltck | ---- | No path
From clk48m[0] | ---- | No path
------------------------------------------------------------------------------------------------------
2.2 Clock "rvltck"
create_clock -name {rvltck} -period 33.33 -waveform {0.000 16.665} [get_ports TCK]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock rvltck | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From rvltck | Target | 33.330 ns | 30.003 MHz
| Actual (all paths) | 12.169 ns | 82.176 MHz
jtaghub_inst/IB_inst2.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock rvltck | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From MON_c[0] | ---- | No path
From clk48m[0] | ---- | False path
------------------------------------------------------------------------------------------------------
2.3 Clock "clk48m[0]"
create_clock -name {clk48m[0]} -period 20.8333333333333 [get_nets {clk48m[0]}]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock clk48m[0] | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From clk48m[0] | Target | 20.833 ns | 48.000 MHz
| Actual (all paths) | 4.792 ns | 208.681 MHz
secured_pin_0_932_64 (MPW) | (50% duty cycle) | 3.226 ns | 309.981 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock clk48m[0] | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From MON_c[0] | ---- | No path
From rvltck | ---- | False path
------------------------------------------------------------------------------------------------------
3 TIMING ANALYSIS SUMMARY
3.1 Overall (Setup and Hold)
3.1.1 Constraint Coverage
Constraint Coverage: 80.0148%
3.1.2 Timing Errors
Timing Errors: 0 endpoints (setup), 0 endpoints (hold)
3.1.3 Total Timing Score
Total Negative Slack: 0.000 ns (setup), 0.000 ns (hold)
3.2 Setup Summary Report
-------------------------------------------------------
Listing 10 End Points | Slack
-------------------------------------------------------
secured_pin_0_465_15 | 16.041 ns
secured_pin_0_462_15 | 16.041 ns
secured_pin_0_456_15 | 16.041 ns
secured_pin_0_455_15 | 16.042 ns
secured_pin_0_454_15 | 16.042 ns
secured_pin_0_453_15 | 16.042 ns
secured_pin_0_463_15 | 16.047 ns
secured_pin_0_459_15 | 16.073 ns
secured_pin_0_458_15 | 16.073 ns
secured_pin_0_457_15 | 16.073 ns
-------------------------------------------------------
|
Setup # of endpoints with negative slack:| 0
|
-------------------------------------------------------
3.3 Hold Summary Report
-------------------------------------------------------
Listing 10 End Points | Slack
-------------------------------------------------------
secured_pin_0_501_11 | 0.165 ns
secured_pin_0_495_11 | 0.165 ns
secured_pin_0_493_11 | 0.165 ns
secured_pin_0_208_11 | 0.165 ns
secured_pin_0_499_11 | 0.182 ns
secured_pin_0_284_11 | 0.187 ns
secured_pin_0_279_11 | 0.187 ns
secured_pin_0_210_11 | 0.187 ns
secured_pin_0_209_11 | 0.187 ns
secured_pin_0_159_11 | 0.187 ns
-------------------------------------------------------
|
Hold # of endpoints with negative slack: | 0
|
-------------------------------------------------------
3.4 Unconstrained Report
3.4.1 Unconstrained Start/End Points
Clocked but unconstrained timing start points
--------------------------------------------------
There is no start point satisfying reporting criteria
Clocked but unconstrained timing end points
-------------------------------------------------------------------
Listing 4 End Points | Type
-------------------------------------------------------------------
secured_pin_0_255_9 | No arrival or required
secured_pin_0_406_9 | No arrival or required
i_RAM_DP1/lscc_ram_dp_inst/mem_main/NON_MIX.ADDR_ROUTE[0].DATA_ROUTE[0].genblk3.f_rd_en_r.ff_inst/DF
| No arrival time
i_RAM_DP1/lscc_ram_dp_inst/mem_main/NON_MIX.ADDR_ROUTE[0].DATA_ROUTE[0].mem_init.u_mem0/LIFCL_MEM.pdp16k.PDP16K_MODE_inst/CER
| No arrival time
-------------------------------------------------------------------
|
Number of unconstrained timing end poin |
ts | 4
|
-------------------------------------------------------------------
3.4.2 Start/End Points Without Timing Constraints
I/O ports without constraint
----------------------------
Possible constraints to use on I/O ports are:
set_input_delay,
set_output_delay,
set_max_delay,
create_clock,
create_generated_clock,
...
-------------------------------------------------------------------
Listing 10 Start or End Points | Type
-------------------------------------------------------------------
SW[2] | input
SW[1] | input
SW[3] | input
SEG_OUT[7] | output
SEG_OUT[6] | output
SEG_OUT[5] | output
SEG_OUT[4] | output
SEG_OUT[3] | output
SEG_OUT[2] | output
SEG_OUT[1] | output
-------------------------------------------------------------------
|
Number of I/O ports without constraint | 41
|
-------------------------------------------------------------------
Registers without clock definition
Define the clock for these registers.
--------------------------------------------------
There is no instance satisfying reporting criteria
4 DETAILED REPORT
4.1 Setup Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++ Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : secured_pin_0_408_20 (SLICE_R29C32D)
Path End : secured_pin_0_465_15 (SLICE_R34C24B)
Source Clock : clk48m[0] (R)
Destination Clock: clk48m[0] (R)
Logic Level : 6
Delay Ratio : 67.2% (route), 32.8% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 20.833 ns
Path Slack : 16.041 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_408_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":2.484,
"delay":2.484
}
]
}
]]>
Name Cell/Site Name Delay Name Delay Arrival/Required Time Fanout
---------------------------------------- ---------------- ------------- ----- --------------------- ------
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93
NET DELAY 2.484 2.484 233
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"secured_pin_0_408_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_465_15",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.IfbJrh5D2aL7lbqkJm2I[12].SLICE_465/CE"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_408_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/CLK"
},
"pin1":
{
"log_name":"secured_pin_0_408_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/Q0"
},
"arrive":2.819,
"delay":0.335
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_121",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ne3nFILyd5q303pD9C8l[2]"
},
"arrive":3.221,
"delay":0.402
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_792_4",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_792/D0"
},
"pin1":
{
"log_name":"secured_pin_0_792_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_792/F0"
},
"arrive":3.454,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_467",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.NFIzFfl7"
},
"arrive":3.882,
"delay":0.428
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_777_7",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_777/A0"
},
"pin1":
{
"log_name":"secured_pin_0_777_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_777/F0"
},
"arrive":4.115,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_107",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.wen"
},
"arrive":4.632,
"delay":0.517
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_913_5",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.decode_u.SLICE_913/C0"
},
"pin1":
{
"log_name":"secured_pin_0_913_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.decode_u.SLICE_913/F0"
},
"arrive":4.865,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_30",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.wen_te[0]"
},
"arrive":5.166,
"delay":0.301
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_857_6",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_857/B0"
},
"pin1":
{
"log_name":"secured_pin_0_857_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_857/F0"
},
"arrive":5.399,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_125",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.NcxKsbwtICyECy8IeK8kG17"
},
"arrive":6.100,
"delay":0.701
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_850_5",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_850/C0"
},
"pin1":
{
"log_name":"secured_pin_0_850_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_850/F0"
},
"arrive":6.333,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_128",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.Ndpgbw4d0CK8JxgJG6b7Eo1CnJkreaFDr"
},
"arrive":7.063,
"delay":0.730
}
]
}
]]>
secured_pin_0_408_13->secured_pin_0_408_20
SLICE_R29C32D REG_DEL 0.335 2.819 5
Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_121
NET DELAY 0.402 3.221 5
secured_pin_0_792_4->secured_pin_0_792_19
SLICE_R32C32C CTOF_DEL 0.233 3.454 1
Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_467
NET DELAY 0.428 3.882 1
secured_pin_0_777_7->secured_pin_0_777_19
SLICE_R33C33D CTOF_DEL 0.233 4.115 8
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_107
NET DELAY 0.517 4.632 8
secured_pin_0_913_5->secured_pin_0_913_19
SLICE_R36C31B CTOF_DEL 0.233 4.865 4
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_30
NET DELAY 0.301 5.166 4
secured_pin_0_857_6->secured_pin_0_857_19
SLICE_R35C31B CTOF_DEL 0.233 5.399 2
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_125
NET DELAY 0.701 6.100 2
secured_pin_0_850_5->secured_pin_0_850_19
SLICE_R32C25A CTOF_DEL 0.233 6.333 16
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_128 ( CE )
NET DELAY 0.730 7.063 16
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_465_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.IfbJrh5D2aL7lbqkJm2I[12].SLICE_465/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":20.833,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":23.317,
"delay":2.484
}
]
}
]]>
CONSTRAINT 0.000 20.833 1
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 20.833 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93 ( CLK )
NET DELAY 2.484 23.317 233
Uncertainty 0.000 23.317
Setup time 0.213 23.104
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Required Time 23.104
Arrival Time -7.063
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Path Slack (Passed) 16.041
++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : secured_pin_0_408_20 (SLICE_R29C32D)
Path End : secured_pin_0_462_15 (SLICE_R34C24C)
Source Clock : clk48m[0] (R)
Destination Clock: clk48m[0] (R)
Logic Level : 6
Delay Ratio : 67.2% (route), 32.8% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 20.833 ns
Path Slack : 16.041 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_408_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":2.484,
"delay":2.484
}
]
}
]]>
Name Cell/Site Name Delay Name Delay Arrival/Required Time Fanout
---------------------------------------- ---------------- ------------- ----- --------------------- ------
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93
NET DELAY 2.484 2.484 233
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"secured_pin_0_408_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_462_15",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.IfbJrh5D2aL7lbqkJm2I[9].SLICE_462/CE"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_408_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/CLK"
},
"pin1":
{
"log_name":"secured_pin_0_408_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/Q0"
},
"arrive":2.819,
"delay":0.335
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_121",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ne3nFILyd5q303pD9C8l[2]"
},
"arrive":3.221,
"delay":0.402
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_792_4",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_792/D0"
},
"pin1":
{
"log_name":"secured_pin_0_792_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_792/F0"
},
"arrive":3.454,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_467",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.NFIzFfl7"
},
"arrive":3.882,
"delay":0.428
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_777_7",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_777/A0"
},
"pin1":
{
"log_name":"secured_pin_0_777_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_777/F0"
},
"arrive":4.115,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_107",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.wen"
},
"arrive":4.632,
"delay":0.517
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_913_5",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.decode_u.SLICE_913/C0"
},
"pin1":
{
"log_name":"secured_pin_0_913_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.decode_u.SLICE_913/F0"
},
"arrive":4.865,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_30",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.wen_te[0]"
},
"arrive":5.166,
"delay":0.301
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_857_6",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_857/B0"
},
"pin1":
{
"log_name":"secured_pin_0_857_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_857/F0"
},
"arrive":5.399,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_125",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.NcxKsbwtICyECy8IeK8kG17"
},
"arrive":6.100,
"delay":0.701
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_850_5",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_850/C0"
},
"pin1":
{
"log_name":"secured_pin_0_850_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_850/F0"
},
"arrive":6.333,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_128",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.Ndpgbw4d0CK8JxgJG6b7Eo1CnJkreaFDr"
},
"arrive":7.063,
"delay":0.730
}
]
}
]]>
secured_pin_0_408_13->secured_pin_0_408_20
SLICE_R29C32D REG_DEL 0.335 2.819 5
Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_121
NET DELAY 0.402 3.221 5
secured_pin_0_792_4->secured_pin_0_792_19
SLICE_R32C32C CTOF_DEL 0.233 3.454 1
Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_467
NET DELAY 0.428 3.882 1
secured_pin_0_777_7->secured_pin_0_777_19
SLICE_R33C33D CTOF_DEL 0.233 4.115 8
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_107
NET DELAY 0.517 4.632 8
secured_pin_0_913_5->secured_pin_0_913_19
SLICE_R36C31B CTOF_DEL 0.233 4.865 4
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_30
NET DELAY 0.301 5.166 4
secured_pin_0_857_6->secured_pin_0_857_19
SLICE_R35C31B CTOF_DEL 0.233 5.399 2
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_125
NET DELAY 0.701 6.100 2
secured_pin_0_850_5->secured_pin_0_850_19
SLICE_R32C25A CTOF_DEL 0.233 6.333 16
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_128 ( CE )
NET DELAY 0.730 7.063 16
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_462_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.IfbJrh5D2aL7lbqkJm2I[9].SLICE_462/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":20.833,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":23.317,
"delay":2.484
}
]
}
]]>
CONSTRAINT 0.000 20.833 1
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 20.833 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93 ( CLK )
NET DELAY 2.484 23.317 233
Uncertainty 0.000 23.317
Setup time 0.213 23.104
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Required Time 23.104
Arrival Time -7.063
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Path Slack (Passed) 16.041
++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : secured_pin_0_408_20 (SLICE_R29C32D)
Path End : secured_pin_0_456_15 (SLICE_R34C24D)
Source Clock : clk48m[0] (R)
Destination Clock: clk48m[0] (R)
Logic Level : 6
Delay Ratio : 67.2% (route), 32.8% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 20.833 ns
Path Slack : 16.041 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_408_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":2.484,
"delay":2.484
}
]
}
]]>
Name Cell/Site Name Delay Name Delay Arrival/Required Time Fanout
---------------------------------------- ---------------- ------------- ----- --------------------- ------
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93
NET DELAY 2.484 2.484 233
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"secured_pin_0_408_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_456_15",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.IfbJrh5D2aL7lbqkJm2I[3].SLICE_456/CE"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_408_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/CLK"
},
"pin1":
{
"log_name":"secured_pin_0_408_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/Q0"
},
"arrive":2.819,
"delay":0.335
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_121",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ne3nFILyd5q303pD9C8l[2]"
},
"arrive":3.221,
"delay":0.402
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_792_4",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_792/D0"
},
"pin1":
{
"log_name":"secured_pin_0_792_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_792/F0"
},
"arrive":3.454,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_467",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.NFIzFfl7"
},
"arrive":3.882,
"delay":0.428
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_777_7",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_777/A0"
},
"pin1":
{
"log_name":"secured_pin_0_777_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_777/F0"
},
"arrive":4.115,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_107",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.wen"
},
"arrive":4.632,
"delay":0.517
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_913_5",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.decode_u.SLICE_913/C0"
},
"pin1":
{
"log_name":"secured_pin_0_913_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.decode_u.SLICE_913/F0"
},
"arrive":4.865,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_30",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.wen_te[0]"
},
"arrive":5.166,
"delay":0.301
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_857_6",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_857/B0"
},
"pin1":
{
"log_name":"secured_pin_0_857_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_857/F0"
},
"arrive":5.399,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_125",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.NcxKsbwtICyECy8IeK8kG17"
},
"arrive":6.100,
"delay":0.701
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_850_5",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_850/C0"
},
"pin1":
{
"log_name":"secured_pin_0_850_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_850/F0"
},
"arrive":6.333,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_128",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.Ndpgbw4d0CK8JxgJG6b7Eo1CnJkreaFDr"
},
"arrive":7.063,
"delay":0.730
}
]
}
]]>
secured_pin_0_408_13->secured_pin_0_408_20
SLICE_R29C32D REG_DEL 0.335 2.819 5
Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_121
NET DELAY 0.402 3.221 5
secured_pin_0_792_4->secured_pin_0_792_19
SLICE_R32C32C CTOF_DEL 0.233 3.454 1
Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_467
NET DELAY 0.428 3.882 1
secured_pin_0_777_7->secured_pin_0_777_19
SLICE_R33C33D CTOF_DEL 0.233 4.115 8
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_107
NET DELAY 0.517 4.632 8
secured_pin_0_913_5->secured_pin_0_913_19
SLICE_R36C31B CTOF_DEL 0.233 4.865 4
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_30
NET DELAY 0.301 5.166 4
secured_pin_0_857_6->secured_pin_0_857_19
SLICE_R35C31B CTOF_DEL 0.233 5.399 2
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_125
NET DELAY 0.701 6.100 2
secured_pin_0_850_5->secured_pin_0_850_19
SLICE_R32C25A CTOF_DEL 0.233 6.333 16
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_128 ( CE )
NET DELAY 0.730 7.063 16
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_456_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.IfbJrh5D2aL7lbqkJm2I[3].SLICE_456/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":20.833,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":23.317,
"delay":2.484
}
]
}
]]>
CONSTRAINT 0.000 20.833 1
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 20.833 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93 ( CLK )
NET DELAY 2.484 23.317 233
Uncertainty 0.000 23.317
Setup time 0.213 23.104
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Required Time 23.104
Arrival Time -7.063
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Path Slack (Passed) 16.041
++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : secured_pin_0_408_20 (SLICE_R29C32D)
Path End : secured_pin_0_455_15 (SLICE_R36C26B)
Source Clock : clk48m[0] (R)
Destination Clock: clk48m[0] (R)
Logic Level : 6
Delay Ratio : 67.2% (route), 32.8% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 20.833 ns
Path Slack : 16.042 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_408_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":2.484,
"delay":2.484
}
]
}
]]>
Name Cell/Site Name Delay Name Delay Arrival/Required Time Fanout
---------------------------------------- ---------------- ------------- ----- --------------------- ------
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93
NET DELAY 2.484 2.484 233
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"secured_pin_0_408_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_455_15",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.IfbJrh5D2aL7lbqkJm2I[2].SLICE_455/CE"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_408_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/CLK"
},
"pin1":
{
"log_name":"secured_pin_0_408_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/Q0"
},
"arrive":2.819,
"delay":0.335
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_121",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ne3nFILyd5q303pD9C8l[2]"
},
"arrive":3.221,
"delay":0.402
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_792_4",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_792/D0"
},
"pin1":
{
"log_name":"secured_pin_0_792_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_792/F0"
},
"arrive":3.454,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_467",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.NFIzFfl7"
},
"arrive":3.882,
"delay":0.428
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_777_7",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_777/A0"
},
"pin1":
{
"log_name":"secured_pin_0_777_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_777/F0"
},
"arrive":4.115,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_107",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.wen"
},
"arrive":4.632,
"delay":0.517
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_913_5",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.decode_u.SLICE_913/C0"
},
"pin1":
{
"log_name":"secured_pin_0_913_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.decode_u.SLICE_913/F0"
},
"arrive":4.865,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_30",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.wen_te[0]"
},
"arrive":5.166,
"delay":0.301
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_857_6",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_857/B0"
},
"pin1":
{
"log_name":"secured_pin_0_857_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_857/F0"
},
"arrive":5.399,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_125",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.NcxKsbwtICyECy8IeK8kG17"
},
"arrive":6.100,
"delay":0.701
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_850_5",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_850/C0"
},
"pin1":
{
"log_name":"secured_pin_0_850_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_850/F0"
},
"arrive":6.333,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_128",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.Ndpgbw4d0CK8JxgJG6b7Eo1CnJkreaFDr"
},
"arrive":7.062,
"delay":0.729
}
]
}
]]>
secured_pin_0_408_13->secured_pin_0_408_20
SLICE_R29C32D REG_DEL 0.335 2.819 5
Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_121
NET DELAY 0.402 3.221 5
secured_pin_0_792_4->secured_pin_0_792_19
SLICE_R32C32C CTOF_DEL 0.233 3.454 1
Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_467
NET DELAY 0.428 3.882 1
secured_pin_0_777_7->secured_pin_0_777_19
SLICE_R33C33D CTOF_DEL 0.233 4.115 8
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_107
NET DELAY 0.517 4.632 8
secured_pin_0_913_5->secured_pin_0_913_19
SLICE_R36C31B CTOF_DEL 0.233 4.865 4
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_30
NET DELAY 0.301 5.166 4
secured_pin_0_857_6->secured_pin_0_857_19
SLICE_R35C31B CTOF_DEL 0.233 5.399 2
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_125
NET DELAY 0.701 6.100 2
secured_pin_0_850_5->secured_pin_0_850_19
SLICE_R32C25A CTOF_DEL 0.233 6.333 16
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_128 ( CE )
NET DELAY 0.729 7.062 16
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_455_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.IfbJrh5D2aL7lbqkJm2I[2].SLICE_455/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":20.833,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":23.317,
"delay":2.484
}
]
}
]]>
CONSTRAINT 0.000 20.833 1
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 20.833 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93 ( CLK )
NET DELAY 2.484 23.317 233
Uncertainty 0.000 23.317
Setup time 0.213 23.104
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Required Time 23.104
Arrival Time -7.062
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Path Slack (Passed) 16.042
++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : secured_pin_0_408_20 (SLICE_R29C32D)
Path End : secured_pin_0_454_15 (SLICE_R36C26C)
Source Clock : clk48m[0] (R)
Destination Clock: clk48m[0] (R)
Logic Level : 6
Delay Ratio : 67.2% (route), 32.8% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 20.833 ns
Path Slack : 16.042 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_408_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":2.484,
"delay":2.484
}
]
}
]]>
Name Cell/Site Name Delay Name Delay Arrival/Required Time Fanout
---------------------------------------- ---------------- ------------- ----- --------------------- ------
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93
NET DELAY 2.484 2.484 233
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"secured_pin_0_408_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_454_15",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.IfbJrh5D2aL7lbqkJm2I[1].SLICE_454/CE"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_408_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/CLK"
},
"pin1":
{
"log_name":"secured_pin_0_408_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/Q0"
},
"arrive":2.819,
"delay":0.335
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_121",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ne3nFILyd5q303pD9C8l[2]"
},
"arrive":3.221,
"delay":0.402
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_792_4",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_792/D0"
},
"pin1":
{
"log_name":"secured_pin_0_792_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_792/F0"
},
"arrive":3.454,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_467",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.NFIzFfl7"
},
"arrive":3.882,
"delay":0.428
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_777_7",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_777/A0"
},
"pin1":
{
"log_name":"secured_pin_0_777_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_777/F0"
},
"arrive":4.115,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_107",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.wen"
},
"arrive":4.632,
"delay":0.517
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_913_5",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.decode_u.SLICE_913/C0"
},
"pin1":
{
"log_name":"secured_pin_0_913_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.decode_u.SLICE_913/F0"
},
"arrive":4.865,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_30",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.wen_te[0]"
},
"arrive":5.166,
"delay":0.301
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_857_6",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_857/B0"
},
"pin1":
{
"log_name":"secured_pin_0_857_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_857/F0"
},
"arrive":5.399,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_125",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.NcxKsbwtICyECy8IeK8kG17"
},
"arrive":6.100,
"delay":0.701
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_850_5",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_850/C0"
},
"pin1":
{
"log_name":"secured_pin_0_850_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_850/F0"
},
"arrive":6.333,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_128",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.Ndpgbw4d0CK8JxgJG6b7Eo1CnJkreaFDr"
},
"arrive":7.062,
"delay":0.729
}
]
}
]]>
secured_pin_0_408_13->secured_pin_0_408_20
SLICE_R29C32D REG_DEL 0.335 2.819 5
Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_121
NET DELAY 0.402 3.221 5
secured_pin_0_792_4->secured_pin_0_792_19
SLICE_R32C32C CTOF_DEL 0.233 3.454 1
Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_467
NET DELAY 0.428 3.882 1
secured_pin_0_777_7->secured_pin_0_777_19
SLICE_R33C33D CTOF_DEL 0.233 4.115 8
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_107
NET DELAY 0.517 4.632 8
secured_pin_0_913_5->secured_pin_0_913_19
SLICE_R36C31B CTOF_DEL 0.233 4.865 4
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_30
NET DELAY 0.301 5.166 4
secured_pin_0_857_6->secured_pin_0_857_19
SLICE_R35C31B CTOF_DEL 0.233 5.399 2
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_125
NET DELAY 0.701 6.100 2
secured_pin_0_850_5->secured_pin_0_850_19
SLICE_R32C25A CTOF_DEL 0.233 6.333 16
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_128 ( CE )
NET DELAY 0.729 7.062 16
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_454_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.IfbJrh5D2aL7lbqkJm2I[1].SLICE_454/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":20.833,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":23.317,
"delay":2.484
}
]
}
]]>
CONSTRAINT 0.000 20.833 1
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 20.833 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93 ( CLK )
NET DELAY 2.484 23.317 233
Uncertainty 0.000 23.317
Setup time 0.213 23.104
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Required Time 23.104
Arrival Time -7.062
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Path Slack (Passed) 16.042
++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : secured_pin_0_408_20 (SLICE_R29C32D)
Path End : secured_pin_0_453_15 (SLICE_R36C26D)
Source Clock : clk48m[0] (R)
Destination Clock: clk48m[0] (R)
Logic Level : 6
Delay Ratio : 67.2% (route), 32.8% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 20.833 ns
Path Slack : 16.042 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_408_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":2.484,
"delay":2.484
}
]
}
]]>
Name Cell/Site Name Delay Name Delay Arrival/Required Time Fanout
---------------------------------------- ---------------- ------------- ----- --------------------- ------
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93
NET DELAY 2.484 2.484 233
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"secured_pin_0_408_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_453_15",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.IfbJrh5D2aL7lbqkJm2I[0].SLICE_453/CE"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_408_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/CLK"
},
"pin1":
{
"log_name":"secured_pin_0_408_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/Q0"
},
"arrive":2.819,
"delay":0.335
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_121",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ne3nFILyd5q303pD9C8l[2]"
},
"arrive":3.221,
"delay":0.402
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_792_4",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_792/D0"
},
"pin1":
{
"log_name":"secured_pin_0_792_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_792/F0"
},
"arrive":3.454,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_467",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.NFIzFfl7"
},
"arrive":3.882,
"delay":0.428
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_777_7",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_777/A0"
},
"pin1":
{
"log_name":"secured_pin_0_777_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_777/F0"
},
"arrive":4.115,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_107",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.wen"
},
"arrive":4.632,
"delay":0.517
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_913_5",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.decode_u.SLICE_913/C0"
},
"pin1":
{
"log_name":"secured_pin_0_913_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.decode_u.SLICE_913/F0"
},
"arrive":4.865,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_30",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.wen_te[0]"
},
"arrive":5.166,
"delay":0.301
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_857_6",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_857/B0"
},
"pin1":
{
"log_name":"secured_pin_0_857_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_857/F0"
},
"arrive":5.399,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_125",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.NcxKsbwtICyECy8IeK8kG17"
},
"arrive":6.100,
"delay":0.701
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_850_5",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_850/C0"
},
"pin1":
{
"log_name":"secured_pin_0_850_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_850/F0"
},
"arrive":6.333,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_128",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.Ndpgbw4d0CK8JxgJG6b7Eo1CnJkreaFDr"
},
"arrive":7.062,
"delay":0.729
}
]
}
]]>
secured_pin_0_408_13->secured_pin_0_408_20
SLICE_R29C32D REG_DEL 0.335 2.819 5
Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_121
NET DELAY 0.402 3.221 5
secured_pin_0_792_4->secured_pin_0_792_19
SLICE_R32C32C CTOF_DEL 0.233 3.454 1
Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_467
NET DELAY 0.428 3.882 1
secured_pin_0_777_7->secured_pin_0_777_19
SLICE_R33C33D CTOF_DEL 0.233 4.115 8
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_107
NET DELAY 0.517 4.632 8
secured_pin_0_913_5->secured_pin_0_913_19
SLICE_R36C31B CTOF_DEL 0.233 4.865 4
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_30
NET DELAY 0.301 5.166 4
secured_pin_0_857_6->secured_pin_0_857_19
SLICE_R35C31B CTOF_DEL 0.233 5.399 2
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_125
NET DELAY 0.701 6.100 2
secured_pin_0_850_5->secured_pin_0_850_19
SLICE_R32C25A CTOF_DEL 0.233 6.333 16
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_128 ( CE )
NET DELAY 0.729 7.062 16
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_453_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.IfbJrh5D2aL7lbqkJm2I[0].SLICE_453/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":20.833,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":23.317,
"delay":2.484
}
]
}
]]>
CONSTRAINT 0.000 20.833 1
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 20.833 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93 ( CLK )
NET DELAY 2.484 23.317 233
Uncertainty 0.000 23.317
Setup time 0.213 23.104
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Required Time 23.104
Arrival Time -7.062
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Path Slack (Passed) 16.042
++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : secured_pin_0_408_20 (SLICE_R29C32D)
Path End : secured_pin_0_463_15 (SLICE_R33C24D)
Source Clock : clk48m[0] (R)
Destination Clock: clk48m[0] (R)
Logic Level : 6
Delay Ratio : 67.2% (route), 32.8% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 20.833 ns
Path Slack : 16.047 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_408_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":2.484,
"delay":2.484
}
]
}
]]>
Name Cell/Site Name Delay Name Delay Arrival/Required Time Fanout
---------------------------------------- ---------------- ------------- ----- --------------------- ------
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93
NET DELAY 2.484 2.484 233
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"secured_pin_0_408_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_463_15",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.IfbJrh5D2aL7lbqkJm2I[10].SLICE_463/CE"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_408_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/CLK"
},
"pin1":
{
"log_name":"secured_pin_0_408_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/Q0"
},
"arrive":2.819,
"delay":0.335
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_121",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ne3nFILyd5q303pD9C8l[2]"
},
"arrive":3.221,
"delay":0.402
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_792_4",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_792/D0"
},
"pin1":
{
"log_name":"secured_pin_0_792_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_792/F0"
},
"arrive":3.454,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_467",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.NFIzFfl7"
},
"arrive":3.882,
"delay":0.428
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_777_7",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_777/A0"
},
"pin1":
{
"log_name":"secured_pin_0_777_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_777/F0"
},
"arrive":4.115,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_107",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.wen"
},
"arrive":4.632,
"delay":0.517
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_913_5",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.decode_u.SLICE_913/C0"
},
"pin1":
{
"log_name":"secured_pin_0_913_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.decode_u.SLICE_913/F0"
},
"arrive":4.865,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_30",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.wen_te[0]"
},
"arrive":5.166,
"delay":0.301
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_857_6",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_857/B0"
},
"pin1":
{
"log_name":"secured_pin_0_857_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_857/F0"
},
"arrive":5.399,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_125",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.NcxKsbwtICyECy8IeK8kG17"
},
"arrive":6.100,
"delay":0.701
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_850_5",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_850/C0"
},
"pin1":
{
"log_name":"secured_pin_0_850_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_850/F0"
},
"arrive":6.333,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_128",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.Ndpgbw4d0CK8JxgJG6b7Eo1CnJkreaFDr"
},
"arrive":7.057,
"delay":0.724
}
]
}
]]>
secured_pin_0_408_13->secured_pin_0_408_20
SLICE_R29C32D REG_DEL 0.335 2.819 5
Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_121
NET DELAY 0.402 3.221 5
secured_pin_0_792_4->secured_pin_0_792_19
SLICE_R32C32C CTOF_DEL 0.233 3.454 1
Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_467
NET DELAY 0.428 3.882 1
secured_pin_0_777_7->secured_pin_0_777_19
SLICE_R33C33D CTOF_DEL 0.233 4.115 8
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_107
NET DELAY 0.517 4.632 8
secured_pin_0_913_5->secured_pin_0_913_19
SLICE_R36C31B CTOF_DEL 0.233 4.865 4
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_30
NET DELAY 0.301 5.166 4
secured_pin_0_857_6->secured_pin_0_857_19
SLICE_R35C31B CTOF_DEL 0.233 5.399 2
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_125
NET DELAY 0.701 6.100 2
secured_pin_0_850_5->secured_pin_0_850_19
SLICE_R32C25A CTOF_DEL 0.233 6.333 16
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_128 ( CE )
NET DELAY 0.724 7.057 16
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_463_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.IfbJrh5D2aL7lbqkJm2I[10].SLICE_463/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":20.833,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":23.317,
"delay":2.484
}
]
}
]]>
CONSTRAINT 0.000 20.833 1
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 20.833 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93 ( CLK )
NET DELAY 2.484 23.317 233
Uncertainty 0.000 23.317
Setup time 0.213 23.104
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Required Time 23.104
Arrival Time -7.057
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Path Slack (Passed) 16.047
++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : secured_pin_0_408_20 (SLICE_R29C32D)
Path End : secured_pin_0_459_15 (SLICE_R35C25D)
Source Clock : clk48m[0] (R)
Destination Clock: clk48m[0] (R)
Logic Level : 6
Delay Ratio : 67.0% (route), 33.0% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 20.833 ns
Path Slack : 16.073 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_408_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":2.484,
"delay":2.484
}
]
}
]]>
Name Cell/Site Name Delay Name Delay Arrival/Required Time Fanout
---------------------------------------- ---------------- ------------- ----- --------------------- ------
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93
NET DELAY 2.484 2.484 233
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"secured_pin_0_408_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_459_15",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.IfbJrh5D2aL7lbqkJm2I[6].SLICE_459/CE"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_408_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/CLK"
},
"pin1":
{
"log_name":"secured_pin_0_408_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/Q0"
},
"arrive":2.819,
"delay":0.335
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_121",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ne3nFILyd5q303pD9C8l[2]"
},
"arrive":3.221,
"delay":0.402
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_792_4",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_792/D0"
},
"pin1":
{
"log_name":"secured_pin_0_792_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_792/F0"
},
"arrive":3.454,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_467",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.NFIzFfl7"
},
"arrive":3.882,
"delay":0.428
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_777_7",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_777/A0"
},
"pin1":
{
"log_name":"secured_pin_0_777_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_777/F0"
},
"arrive":4.115,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_107",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.wen"
},
"arrive":4.632,
"delay":0.517
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_913_5",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.decode_u.SLICE_913/C0"
},
"pin1":
{
"log_name":"secured_pin_0_913_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.decode_u.SLICE_913/F0"
},
"arrive":4.865,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_30",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.wen_te[0]"
},
"arrive":5.166,
"delay":0.301
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_857_6",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_857/B0"
},
"pin1":
{
"log_name":"secured_pin_0_857_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_857/F0"
},
"arrive":5.399,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_125",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.NcxKsbwtICyECy8IeK8kG17"
},
"arrive":6.100,
"delay":0.701
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_850_5",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_850/C0"
},
"pin1":
{
"log_name":"secured_pin_0_850_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_850/F0"
},
"arrive":6.333,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_128",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.Ndpgbw4d0CK8JxgJG6b7Eo1CnJkreaFDr"
},
"arrive":7.031,
"delay":0.698
}
]
}
]]>
secured_pin_0_408_13->secured_pin_0_408_20
SLICE_R29C32D REG_DEL 0.335 2.819 5
Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_121
NET DELAY 0.402 3.221 5
secured_pin_0_792_4->secured_pin_0_792_19
SLICE_R32C32C CTOF_DEL 0.233 3.454 1
Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_467
NET DELAY 0.428 3.882 1
secured_pin_0_777_7->secured_pin_0_777_19
SLICE_R33C33D CTOF_DEL 0.233 4.115 8
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_107
NET DELAY 0.517 4.632 8
secured_pin_0_913_5->secured_pin_0_913_19
SLICE_R36C31B CTOF_DEL 0.233 4.865 4
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_30
NET DELAY 0.301 5.166 4
secured_pin_0_857_6->secured_pin_0_857_19
SLICE_R35C31B CTOF_DEL 0.233 5.399 2
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_125
NET DELAY 0.701 6.100 2
secured_pin_0_850_5->secured_pin_0_850_19
SLICE_R32C25A CTOF_DEL 0.233 6.333 16
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_128 ( CE )
NET DELAY 0.698 7.031 16
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_459_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.IfbJrh5D2aL7lbqkJm2I[6].SLICE_459/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":20.833,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":23.317,
"delay":2.484
}
]
}
]]>
CONSTRAINT 0.000 20.833 1
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 20.833 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93 ( CLK )
NET DELAY 2.484 23.317 233
Uncertainty 0.000 23.317
Setup time 0.213 23.104
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Required Time 23.104
Arrival Time -7.031
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Path Slack (Passed) 16.073
++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : secured_pin_0_408_20 (SLICE_R29C32D)
Path End : secured_pin_0_458_15 (SLICE_R38C25C)
Source Clock : clk48m[0] (R)
Destination Clock: clk48m[0] (R)
Logic Level : 6
Delay Ratio : 67.0% (route), 33.0% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 20.833 ns
Path Slack : 16.073 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_408_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":2.484,
"delay":2.484
}
]
}
]]>
Name Cell/Site Name Delay Name Delay Arrival/Required Time Fanout
---------------------------------------- ---------------- ------------- ----- --------------------- ------
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93
NET DELAY 2.484 2.484 233
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"secured_pin_0_408_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_458_15",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.IfbJrh5D2aL7lbqkJm2I[5].SLICE_458/CE"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_408_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/CLK"
},
"pin1":
{
"log_name":"secured_pin_0_408_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/Q0"
},
"arrive":2.819,
"delay":0.335
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_121",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ne3nFILyd5q303pD9C8l[2]"
},
"arrive":3.221,
"delay":0.402
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_792_4",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_792/D0"
},
"pin1":
{
"log_name":"secured_pin_0_792_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_792/F0"
},
"arrive":3.454,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_467",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.NFIzFfl7"
},
"arrive":3.882,
"delay":0.428
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_777_7",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_777/A0"
},
"pin1":
{
"log_name":"secured_pin_0_777_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_777/F0"
},
"arrive":4.115,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_107",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.wen"
},
"arrive":4.632,
"delay":0.517
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_913_5",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.decode_u.SLICE_913/C0"
},
"pin1":
{
"log_name":"secured_pin_0_913_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.decode_u.SLICE_913/F0"
},
"arrive":4.865,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_30",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.wen_te[0]"
},
"arrive":5.166,
"delay":0.301
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_857_6",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_857/B0"
},
"pin1":
{
"log_name":"secured_pin_0_857_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_857/F0"
},
"arrive":5.399,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_125",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.NcxKsbwtICyECy8IeK8kG17"
},
"arrive":6.100,
"delay":0.701
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_850_5",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_850/C0"
},
"pin1":
{
"log_name":"secured_pin_0_850_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_850/F0"
},
"arrive":6.333,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_128",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.Ndpgbw4d0CK8JxgJG6b7Eo1CnJkreaFDr"
},
"arrive":7.031,
"delay":0.698
}
]
}
]]>
secured_pin_0_408_13->secured_pin_0_408_20
SLICE_R29C32D REG_DEL 0.335 2.819 5
Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_121
NET DELAY 0.402 3.221 5
secured_pin_0_792_4->secured_pin_0_792_19
SLICE_R32C32C CTOF_DEL 0.233 3.454 1
Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_467
NET DELAY 0.428 3.882 1
secured_pin_0_777_7->secured_pin_0_777_19
SLICE_R33C33D CTOF_DEL 0.233 4.115 8
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_107
NET DELAY 0.517 4.632 8
secured_pin_0_913_5->secured_pin_0_913_19
SLICE_R36C31B CTOF_DEL 0.233 4.865 4
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_30
NET DELAY 0.301 5.166 4
secured_pin_0_857_6->secured_pin_0_857_19
SLICE_R35C31B CTOF_DEL 0.233 5.399 2
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_125
NET DELAY 0.701 6.100 2
secured_pin_0_850_5->secured_pin_0_850_19
SLICE_R32C25A CTOF_DEL 0.233 6.333 16
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_128 ( CE )
NET DELAY 0.698 7.031 16
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_458_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.IfbJrh5D2aL7lbqkJm2I[5].SLICE_458/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":20.833,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":23.317,
"delay":2.484
}
]
}
]]>
CONSTRAINT 0.000 20.833 1
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 20.833 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93 ( CLK )
NET DELAY 2.484 23.317 233
Uncertainty 0.000 23.317
Setup time 0.213 23.104
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Required Time 23.104
Arrival Time -7.031
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Path Slack (Passed) 16.073
++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : secured_pin_0_408_20 (SLICE_R29C32D)
Path End : secured_pin_0_457_15 (SLICE_R38C25D)
Source Clock : clk48m[0] (R)
Destination Clock: clk48m[0] (R)
Logic Level : 6
Delay Ratio : 67.0% (route), 33.0% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 20.833 ns
Path Slack : 16.073 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_408_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":2.484,
"delay":2.484
}
]
}
]]>
Name Cell/Site Name Delay Name Delay Arrival/Required Time Fanout
---------------------------------------- ---------------- ------------- ----- --------------------- ------
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93
NET DELAY 2.484 2.484 233
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"secured_pin_0_408_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_457_15",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.IfbJrh5D2aL7lbqkJm2I[4].SLICE_457/CE"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_408_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/CLK"
},
"pin1":
{
"log_name":"secured_pin_0_408_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ie3nFILyd5q303pD9C8l[2].SLICE_408/Q0"
},
"arrive":2.819,
"delay":0.335
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_121",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.Ne3nFILyd5q303pD9C8l[2]"
},
"arrive":3.221,
"delay":0.402
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_792_4",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_792/D0"
},
"pin1":
{
"log_name":"secured_pin_0_792_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_792/F0"
},
"arrive":3.454,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_467",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.NFIzFfl7"
},
"arrive":3.882,
"delay":0.428
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_777_7",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_777/A0"
},
"pin1":
{
"log_name":"secured_pin_0_777_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.jtag_int_u.SLICE_777/F0"
},
"arrive":4.115,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_107",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.wen"
},
"arrive":4.632,
"delay":0.517
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_913_5",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.decode_u.SLICE_913/C0"
},
"pin1":
{
"log_name":"secured_pin_0_913_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.decode_u.SLICE_913/F0"
},
"arrive":4.865,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_30",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.wen_te[0]"
},
"arrive":5.166,
"delay":0.301
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_857_6",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_857/B0"
},
"pin1":
{
"log_name":"secured_pin_0_857_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_857/F0"
},
"arrive":5.399,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_125",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.NcxKsbwtICyECy8IeK8kG17"
},
"arrive":6.100,
"delay":0.701
},
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_850_5",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_850/C0"
},
"pin1":
{
"log_name":"secured_pin_0_850_19",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.SLICE_850/F0"
},
"arrive":6.333,
"delay":0.233
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_128",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.Ndpgbw4d0CK8JxgJG6b7Eo1CnJkreaFDr"
},
"arrive":7.031,
"delay":0.698
}
]
}
]]>
secured_pin_0_408_13->secured_pin_0_408_20
SLICE_R29C32D REG_DEL 0.335 2.819 5
Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_121
NET DELAY 0.402 3.221 5
secured_pin_0_792_4->secured_pin_0_792_19
SLICE_R32C32C CTOF_DEL 0.233 3.454 1
Lab1_reveal_coretop_instance/lab1_la0_inst_0/jtag_int_u/secured_signal_2_467
NET DELAY 0.428 3.882 1
secured_pin_0_777_7->secured_pin_0_777_19
SLICE_R33C33D CTOF_DEL 0.233 4.115 8
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_107
NET DELAY 0.517 4.632 8
secured_pin_0_913_5->secured_pin_0_913_19
SLICE_R36C31B CTOF_DEL 0.233 4.865 4
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_30
NET DELAY 0.301 5.166 4
secured_pin_0_857_6->secured_pin_0_857_19
SLICE_R35C31B CTOF_DEL 0.233 5.399 2
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_125
NET DELAY 0.701 6.100 2
secured_pin_0_850_5->secured_pin_0_850_19
SLICE_R32C25A CTOF_DEL 0.233 6.333 16
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/te_0/secured_signal_5_128 ( CE )
NET DELAY 0.698 7.031 16
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_457_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.te_0.IfbJrh5D2aL7lbqkJm2I[4].SLICE_457/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":20.833,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":23.317,
"delay":2.484
}
]
}
]]>
CONSTRAINT 0.000 20.833 1
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 20.833 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93 ( CLK )
NET DELAY 2.484 23.317 233
Uncertainty 0.000 23.317
Setup time 0.213 23.104
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Required Time 23.104
Arrival Time -7.031
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Path Slack (Passed) 16.073
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################
4.2 Hold Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++ Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : freq_cont_reg[7].ff_inst/Q (SLICE_R32C40A)
Path End : secured_pin_0_501_11 (SLICE_R32C40D)
Source Clock : clk48m[0] (R)
Destination Clock: clk48m[0] (R)
Logic Level : 1
Delay Ratio : 33.2% (route), 66.8% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Path Slack : 0.165 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"freq_cont_reg[7].ff_inst/CLK",
"phy_name":"SLICE_15/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":1.543,
"delay":1.543
}
]
}
]]>
Name Cell/Site Name Delay Name Delay Arrival/Required Time Fanout
---------------------------------------- ---------------- ------------- ----- --------------------- ------
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93
NET DELAY 1.543 1.543 233
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"freq_cont_reg[7].ff_inst/Q",
"phy_name":"SLICE_15/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_501_11",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.tu_0.IbvqsJxiwzrIDIH7[4].SLICE_501/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"freq_cont_reg[7].ff_inst/CLK",
"phy_name":"SLICE_15/CLK"
},
"pin1":
{
"log_name":"freq_cont_reg[7].ff_inst/Q",
"phy_name":"SLICE_15/Q0"
},
"arrive":1.720,
"delay":0.177
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_51",
"phy_name":"freq_cont[7]"
},
"arrive":1.808,
"delay":0.088
}
]
}
]]>
freq_cont_reg[7].ff_inst/CLK->freq_cont_reg[7].ff_inst/Q
SLICE_R32C40A REG_DEL 0.177 1.720 4
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_51 ( M0 )
NET DELAY 0.088 1.808 4
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_501_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.tu_0.IbvqsJxiwzrIDIH7[4].SLICE_501/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":1.543,
"delay":1.543
}
]
}
]]>
CONSTRAINT 0.000 0.000 1
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93 ( CLK )
NET DELAY 1.543 1.543 233
Uncertainty 0.000 1.543
Hold time 0.100 1.643
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Required Time -1.643
Arrival Time 1.808
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Path Slack (Passed) 0.165
++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : secured_pin_0_502_20 (SLICE_R35C40C)
Path End : secured_pin_0_495_11 (SLICE_R35C40D)
Source Clock : clk48m[0] (R)
Destination Clock: clk48m[0] (R)
Logic Level : 1
Delay Ratio : 33.2% (route), 66.8% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Path Slack : 0.165 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_502_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.tu_0.IbvqsJxiwzrIDIH7[5].SLICE_502/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":1.543,
"delay":1.543
}
]
}
]]>
Name Cell/Site Name Delay Name Delay Arrival/Required Time Fanout
---------------------------------------- ---------------- ------------- ----- --------------------- ------
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93
NET DELAY 1.543 1.543 233
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"secured_pin_0_502_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.tu_0.IbvqsJxiwzrIDIH7[5].SLICE_502/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_495_11",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.tu_0.IbvqsJxiwzrIDIH8[5].SLICE_495/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_502_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.tu_0.IbvqsJxiwzrIDIH7[5].SLICE_502/CLK"
},
"pin1":
{
"log_name":"secured_pin_0_502_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.tu_0.IbvqsJxiwzrIDIH7[5].SLICE_502/Q0"
},
"arrive":1.720,
"delay":0.177
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/tu_0/secured_signal_6_63",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.tu_0.NgCKvlB"
},
"arrive":1.808,
"delay":0.088
}
]
}
]]>
secured_pin_0_502_13->secured_pin_0_502_20
SLICE_R35C40C REG_DEL 0.177 1.720 5
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/tu_0/secured_signal_6_63 ( M0 )
NET DELAY 0.088 1.808 5
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_495_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.tu_0.IbvqsJxiwzrIDIH8[5].SLICE_495/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":1.543,
"delay":1.543
}
]
}
]]>
CONSTRAINT 0.000 0.000 1
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93 ( CLK )
NET DELAY 1.543 1.543 233
Uncertainty 0.000 1.543
Hold time 0.100 1.643
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Required Time -1.643
Arrival Time 1.808
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Path Slack (Passed) 0.165
++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : secured_pin_0_500_20 (SLICE_R33C40C)
Path End : secured_pin_0_493_11 (SLICE_R33C40D)
Source Clock : clk48m[0] (R)
Destination Clock: clk48m[0] (R)
Logic Level : 1
Delay Ratio : 33.2% (route), 66.8% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Path Slack : 0.165 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_500_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.tu_0.IbvqsJxiwzrIDIH7[3].SLICE_500/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":1.543,
"delay":1.543
}
]
}
]]>
Name Cell/Site Name Delay Name Delay Arrival/Required Time Fanout
---------------------------------------- ---------------- ------------- ----- --------------------- ------
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93
NET DELAY 1.543 1.543 233
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"secured_pin_0_500_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.tu_0.IbvqsJxiwzrIDIH7[3].SLICE_500/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_493_11",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.tu_0.IbvqsJxiwzrIDIH8[3].SLICE_493/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_500_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.tu_0.IbvqsJxiwzrIDIH7[3].SLICE_500/CLK"
},
"pin1":
{
"log_name":"secured_pin_0_500_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.tu_0.IbvqsJxiwzrIDIH7[3].SLICE_500/Q0"
},
"arrive":1.720,
"delay":0.177
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/tu_0/secured_signal_6_61",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.tu_0.NgCKvl9"
},
"arrive":1.808,
"delay":0.088
}
]
}
]]>
secured_pin_0_500_13->secured_pin_0_500_20
SLICE_R33C40C REG_DEL 0.177 1.720 5
Lab1_reveal_coretop_instance/lab1_la0_inst_0/trig_u/tu_0/secured_signal_6_61 ( M0 )
NET DELAY 0.088 1.808 5
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_493_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.tu_0.IbvqsJxiwzrIDIH8[3].SLICE_493/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":1.543,
"delay":1.543
}
]
}
]]>
CONSTRAINT 0.000 0.000 1
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93 ( CLK )
NET DELAY 1.543 1.543 233
Uncertainty 0.000 1.543
Hold time 0.100 1.643
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Required Time -1.643
Arrival Time 1.808
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Path Slack (Passed) 0.165
++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : i_MULT/lscc_multiplier_inst/genblk1.u_lscc_multiplier_dsp/result_o_mod[1].ff_inst/Q (SLICE_R29C39B)
Path End : secured_pin_0_208_11 (SLICE_R29C39D)
Source Clock : clk48m[0] (R)
Destination Clock: clk48m[0] (R)
Logic Level : 1
Delay Ratio : 33.2% (route), 66.8% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Path Slack : 0.165 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"i_MULT/lscc_multiplier_inst/genblk1.u_lscc_multiplier_dsp/result_o_mod[1].ff_inst/CLK",
"phy_name":"i_MULT.lscc_multiplier_inst.genblk1.u_lscc_multiplier_dsp.result_o_mod[1].SLICE_513/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":1.543,
"delay":1.543
}
]
}
]]>
Name Cell/Site Name Delay Name Delay Arrival/Required Time Fanout
---------------------------------------- ---------------- ------------- ----- --------------------- ------
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93
NET DELAY 1.543 1.543 233
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_MULT/lscc_multiplier_inst/genblk1.u_lscc_multiplier_dsp/result_o_mod[1].ff_inst/Q",
"phy_name":"i_MULT.lscc_multiplier_inst.genblk1.u_lscc_multiplier_dsp.result_o_mod[1].SLICE_513/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_208_11",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.Iiywe27GJcnrher8e[7].SLICE_208/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"i_MULT/lscc_multiplier_inst/genblk1.u_lscc_multiplier_dsp/result_o_mod[1].ff_inst/CLK",
"phy_name":"i_MULT.lscc_multiplier_inst.genblk1.u_lscc_multiplier_dsp.result_o_mod[1].SLICE_513/CLK"
},
"pin1":
{
"log_name":"i_MULT/lscc_multiplier_inst/genblk1.u_lscc_multiplier_dsp/result_o_mod[1].ff_inst/Q",
"phy_name":"i_MULT.lscc_multiplier_inst.genblk1.u_lscc_multiplier_dsp.result_o_mod[1].SLICE_513/Q0"
},
"arrive":1.720,
"delay":0.177
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_60",
"phy_name":"result_o_mod_Q[1]"
},
"arrive":1.808,
"delay":0.088
}
]
}
]]>
i_MULT/lscc_multiplier_inst/genblk1.u_lscc_multiplier_dsp/result_o_mod[1].ff_inst/CLK->i_MULT/lscc_multiplier_inst/genblk1.u_lscc_multiplier_dsp/result_o_mod[1].ff_inst/Q
SLICE_R29C39B REG_DEL 0.177 1.720 1
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_60 ( M0 )
NET DELAY 0.088 1.808 1
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_208_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.Iiywe27GJcnrher8e[7].SLICE_208/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":1.543,
"delay":1.543
}
]
}
]]>
CONSTRAINT 0.000 0.000 1
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93 ( CLK )
NET DELAY 1.543 1.543 233
Uncertainty 0.000 1.543
Hold time 0.100 1.643
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Required Time -1.643
Arrival Time 1.808
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Path Slack (Passed) 0.165
++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : freq_cont_reg[5].ff_inst/Q (SLICE_R32C39D)
Path End : secured_pin_0_499_11 (SLICE_R33C39A)
Source Clock : clk48m[0] (R)
Destination Clock: clk48m[0] (R)
Logic Level : 1
Delay Ratio : 37.2% (route), 62.8% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Path Slack : 0.182 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"freq_cont_reg[5].ff_inst/CLK",
"phy_name":"SLICE_16/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":1.543,
"delay":1.543
}
]
}
]]>
Name Cell/Site Name Delay Name Delay Arrival/Required Time Fanout
---------------------------------------- ---------------- ------------- ----- --------------------- ------
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93
NET DELAY 1.543 1.543 233
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"freq_cont_reg[5].ff_inst/Q",
"phy_name":"SLICE_16/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_499_11",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.tu_0.IbvqsJxiwzrIDIH7[2].SLICE_499/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"freq_cont_reg[5].ff_inst/CLK",
"phy_name":"SLICE_16/CLK"
},
"pin1":
{
"log_name":"freq_cont_reg[5].ff_inst/Q",
"phy_name":"SLICE_16/Q0"
},
"arrive":1.720,
"delay":0.177
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_53",
"phy_name":"freq_cont[5]"
},
"arrive":1.825,
"delay":0.105
}
]
}
]]>
freq_cont_reg[5].ff_inst/CLK->freq_cont_reg[5].ff_inst/Q
SLICE_R32C39D REG_DEL 0.177 1.720 12
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_53 ( M0 )
NET DELAY 0.105 1.825 12
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_499_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.trig_u.tu_0.IbvqsJxiwzrIDIH7[2].SLICE_499/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":1.543,
"delay":1.543
}
]
}
]]>
CONSTRAINT 0.000 0.000 1
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93 ( CLK )
NET DELAY 1.543 1.543 233
Uncertainty 0.000 1.543
Hold time 0.100 1.643
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Required Time -1.643
Arrival Time 1.825
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Path Slack (Passed) 0.182
++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : secured_pin_0_42_22 (SLICE_R40C33A)
Path End : secured_pin_0_284_11 (SLICE_R41C33C)
Source Clock : clk48m[0] (R)
Destination Clock: clk48m[0] (R)
Logic Level : 1
Delay Ratio : 37.6% (route), 62.4% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Path Slack : 0.187 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_42_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.SLICE_42/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":1.543,
"delay":1.543
}
]
}
]]>
Name Cell/Site Name Delay Name Delay Arrival/Required Time Fanout
---------------------------------------- ---------------- ------------- ----- --------------------- ------
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93
NET DELAY 1.543 1.543 233
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"secured_pin_0_42_22",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.SLICE_42/Q1"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_284_11",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.Ib5fslm3pIwbxfDEBylJ3wizx4[8].SLICE_284/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_42_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.SLICE_42/CLK"
},
"pin1":
{
"log_name":"secured_pin_0_42_22",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.SLICE_42/Q1"
},
"arrive":1.722,
"delay":0.179
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_46",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.NcLtEjj5dffxkaEny9yFAcs[8]"
},
"arrive":1.830,
"delay":0.108
}
]
}
]]>
secured_pin_0_42_13->secured_pin_0_42_22 SLICE_R40C33A REG_DEL 0.179 1.722 5
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_46 ( M0 )
NET DELAY 0.108 1.830 5
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_284_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.Ib5fslm3pIwbxfDEBylJ3wizx4[8].SLICE_284/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":1.543,
"delay":1.543
}
]
}
]]>
CONSTRAINT 0.000 0.000 1
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93 ( CLK )
NET DELAY 1.543 1.543 233
Uncertainty 0.000 1.543
Hold time 0.100 1.643
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Required Time -1.643
Arrival Time 1.830
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Path Slack (Passed) 0.187
++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : secured_pin_0_44_20 (SLICE_R40C32C)
Path End : secured_pin_0_279_11 (SLICE_R40C30D)
Source Clock : clk48m[0] (R)
Destination Clock: clk48m[0] (R)
Logic Level : 1
Delay Ratio : 38.3% (route), 61.7% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Path Slack : 0.187 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_44_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.SLICE_44/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":1.543,
"delay":1.543
}
]
}
]]>
Name Cell/Site Name Delay Name Delay Arrival/Required Time Fanout
---------------------------------------- ---------------- ------------- ----- --------------------- ------
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93
NET DELAY 1.543 1.543 233
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"secured_pin_0_44_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.SLICE_44/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_279_11",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.Ib5fslm3pIwbxfDEBylJ3wizx4[3].SLICE_279/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_44_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.SLICE_44/CLK"
},
"pin1":
{
"log_name":"secured_pin_0_44_20",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.SLICE_44/Q0"
},
"arrive":1.720,
"delay":0.177
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_51",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.NcLtEjj5dffxkaEny9yFAcs[3]"
},
"arrive":1.830,
"delay":0.110
}
]
}
]]>
secured_pin_0_44_13->secured_pin_0_44_20 SLICE_R40C32C REG_DEL 0.177 1.720 5
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_51 ( M0 )
NET DELAY 0.110 1.830 5
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_279_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.Ib5fslm3pIwbxfDEBylJ3wizx4[3].SLICE_279/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":1.543,
"delay":1.543
}
]
}
]]>
CONSTRAINT 0.000 0.000 1
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93 ( CLK )
NET DELAY 1.543 1.543 233
Uncertainty 0.000 1.543
Hold time 0.100 1.643
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Required Time -1.643
Arrival Time 1.830
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Path Slack (Passed) 0.187
++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : i_MULT/lscc_multiplier_inst/genblk1.u_lscc_multiplier_dsp/result_o_mod[3].ff_inst/Q (SLICE_R30C40D)
Path End : secured_pin_0_210_11 (SLICE_R30C39D)
Source Clock : clk48m[0] (R)
Destination Clock: clk48m[0] (R)
Logic Level : 1
Delay Ratio : 38.3% (route), 61.7% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Path Slack : 0.187 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"i_MULT/lscc_multiplier_inst/genblk1.u_lscc_multiplier_dsp/result_o_mod[3].ff_inst/CLK",
"phy_name":"i_MULT.lscc_multiplier_inst.genblk1.u_lscc_multiplier_dsp.result_o_mod[3].SLICE_515/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":1.543,
"delay":1.543
}
]
}
]]>
Name Cell/Site Name Delay Name Delay Arrival/Required Time Fanout
---------------------------------------- ---------------- ------------- ----- --------------------- ------
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93
NET DELAY 1.543 1.543 233
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_MULT/lscc_multiplier_inst/genblk1.u_lscc_multiplier_dsp/result_o_mod[3].ff_inst/Q",
"phy_name":"i_MULT.lscc_multiplier_inst.genblk1.u_lscc_multiplier_dsp.result_o_mod[3].SLICE_515/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_210_11",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.Iiywe27GJcnrher8e[9].SLICE_210/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"i_MULT/lscc_multiplier_inst/genblk1.u_lscc_multiplier_dsp/result_o_mod[3].ff_inst/CLK",
"phy_name":"i_MULT.lscc_multiplier_inst.genblk1.u_lscc_multiplier_dsp.result_o_mod[3].SLICE_515/CLK"
},
"pin1":
{
"log_name":"i_MULT/lscc_multiplier_inst/genblk1.u_lscc_multiplier_dsp/result_o_mod[3].ff_inst/Q",
"phy_name":"i_MULT.lscc_multiplier_inst.genblk1.u_lscc_multiplier_dsp.result_o_mod[3].SLICE_515/Q0"
},
"arrive":1.720,
"delay":0.177
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_58",
"phy_name":"result_o_mod_Q[3]"
},
"arrive":1.830,
"delay":0.110
}
]
}
]]>
i_MULT/lscc_multiplier_inst/genblk1.u_lscc_multiplier_dsp/result_o_mod[3].ff_inst/CLK->i_MULT/lscc_multiplier_inst/genblk1.u_lscc_multiplier_dsp/result_o_mod[3].ff_inst/Q
SLICE_R30C40D REG_DEL 0.177 1.720 1
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_58 ( M0 )
NET DELAY 0.110 1.830 1
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_210_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.Iiywe27GJcnrher8e[9].SLICE_210/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":1.543,
"delay":1.543
}
]
}
]]>
CONSTRAINT 0.000 0.000 1
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93 ( CLK )
NET DELAY 1.543 1.543 233
Uncertainty 0.000 1.543
Hold time 0.100 1.643
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Required Time -1.643
Arrival Time 1.830
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Path Slack (Passed) 0.187
++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : i_MULT/lscc_multiplier_inst/genblk1.u_lscc_multiplier_dsp/result_o_mod[2].ff_inst/Q (SLICE_R29C41D)
Path End : secured_pin_0_209_11 (SLICE_R29C39C)
Source Clock : clk48m[0] (R)
Destination Clock: clk48m[0] (R)
Logic Level : 1
Delay Ratio : 38.3% (route), 61.7% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Path Slack : 0.187 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"i_MULT/lscc_multiplier_inst/genblk1.u_lscc_multiplier_dsp/result_o_mod[2].ff_inst/CLK",
"phy_name":"i_MULT.lscc_multiplier_inst.genblk1.u_lscc_multiplier_dsp.result_o_mod[2].SLICE_514/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":1.543,
"delay":1.543
}
]
}
]]>
Name Cell/Site Name Delay Name Delay Arrival/Required Time Fanout
---------------------------------------- ---------------- ------------- ----- --------------------- ------
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93
NET DELAY 1.543 1.543 233
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_MULT/lscc_multiplier_inst/genblk1.u_lscc_multiplier_dsp/result_o_mod[2].ff_inst/Q",
"phy_name":"i_MULT.lscc_multiplier_inst.genblk1.u_lscc_multiplier_dsp.result_o_mod[2].SLICE_514/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_209_11",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.Iiywe27GJcnrher8e[8].SLICE_209/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"i_MULT/lscc_multiplier_inst/genblk1.u_lscc_multiplier_dsp/result_o_mod[2].ff_inst/CLK",
"phy_name":"i_MULT.lscc_multiplier_inst.genblk1.u_lscc_multiplier_dsp.result_o_mod[2].SLICE_514/CLK"
},
"pin1":
{
"log_name":"i_MULT/lscc_multiplier_inst/genblk1.u_lscc_multiplier_dsp/result_o_mod[2].ff_inst/Q",
"phy_name":"i_MULT.lscc_multiplier_inst.genblk1.u_lscc_multiplier_dsp.result_o_mod[2].SLICE_514/Q0"
},
"arrive":1.720,
"delay":0.177
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_59",
"phy_name":"result_o_mod_Q[2]"
},
"arrive":1.830,
"delay":0.110
}
]
}
]]>
i_MULT/lscc_multiplier_inst/genblk1.u_lscc_multiplier_dsp/result_o_mod[2].ff_inst/CLK->i_MULT/lscc_multiplier_inst/genblk1.u_lscc_multiplier_dsp/result_o_mod[2].ff_inst/Q
SLICE_R29C41D REG_DEL 0.177 1.720 1
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_signal_1_59 ( M0 )
NET DELAY 0.110 1.830 1
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_209_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.Iiywe27GJcnrher8e[8].SLICE_209/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":1.543,
"delay":1.543
}
]
}
]]>
CONSTRAINT 0.000 0.000 1
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93 ( CLK )
NET DELAY 1.543 1.543 233
Uncertainty 0.000 1.543
Hold time 0.100 1.643
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Required Time -1.643
Arrival Time 1.830
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Path Slack (Passed) 0.187
++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : secured_pin_0_42_22 (SLICE_R40C33A)
Path End : secured_pin_0_159_11 (SLICE_R42C33D)
Source Clock : clk48m[0] (R)
Destination Clock: clk48m[0] (R)
Logic Level : 1
Delay Ratio : 37.6% (route), 62.4% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Path Slack : 0.187 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_42_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.SLICE_42/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":1.543,
"delay":1.543
}
]
}
]]>
Name Cell/Site Name Delay Name Delay Arrival/Required Time Fanout
---------------------------------------- ---------------- ------------- ----- --------------------- ------
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93
NET DELAY 1.543 1.543 233
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"secured_pin_0_42_22",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.SLICE_42/Q1"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_159_11",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.IJsvJCgIeE1lijpcsh[8].SLICE_159/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"secured_pin_0_42_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.SLICE_42/CLK"
},
"pin1":
{
"log_name":"secured_pin_0_42_22",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.SLICE_42/Q1"
},
"arrive":1.722,
"delay":0.179
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_46",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.NcLtEjj5dffxkaEny9yFAcs[8]"
},
"arrive":1.830,
"delay":0.108
}
]
}
]]>
secured_pin_0_42_13->secured_pin_0_42_22 SLICE_R40C33A REG_DEL 0.179 1.722 5
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_46 ( M0 )
NET DELAY 0.108 1.830 5
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"i_PLL1/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"path_end":
{
"type":"pin",
"log_name":"secured_pin_0_159_13",
"phy_name":"Lab1_reveal_coretop_instance.lab1_la0_inst_0.tm_u.IJsvJCgIeE1lijpcsh[8].SLICE_159/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93",
"phy_name":"clk48m[0]"
},
"arrive":1.543,
"delay":1.543
}
]
}
]]>
CONSTRAINT 0.000 0.000 1
i_PLL1.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_ULC CLOCK LATENCY 0.000 0.000 233
Lab1_reveal_coretop_instance/lab1_la0_inst_0/tm_u/secured_instance_1_135/secured_signal_0_93 ( CLK )
NET DELAY 1.543 1.543 233
Uncertainty 0.000 1.543
Hold time 0.100 1.643
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Required Time -1.643
Arrival Time 1.830
---------------------------------------- ---------------- ------------- ----- --------------------- ------
Path Slack (Passed) 0.187
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################