xcvr |

2018.04.19.15:30:54 | Datasheet

Overview

clk_0 | xcvr

All Components
xcvr_native_a10_0 altera_xcvr_native_a10 17.1
Memory Map

xcvr_native_a10_0
reconfig_avmm

## clk_0

clock_source v17.1

## Parameters
clockFrequency | 125000000
clockFrequencyKnown | true
inputClockFrequency | 0
resetSynchronousEdges | NONE
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## xcvr_native_a10_0

altera_xcvr_native_a10 v17.1

clk_0 | clk | xcvr_native_a10_0
reconfig_clk
clk_reset
reconfig_reset
xcvr_reset_control_0 | rx_analogreset
rx_analogreset
rx_cal_busy
rx_cal_busy
rx_digitalreset
rx_digitalreset
rx_is_lockedtodata
rx_is_lockedtodata
tx_analogreset
tx_analogreset
tx_cal_busy
tx_cal_busy
|  | tx_digitalreset | xcvr_reset_control_0
|  | tx_digitalreset

## Parameters
device_family | ARRIA10
device | 10AX090N2F40E2SG
base_device | NIGHTFURY5
design_environment | QSYS
device_revision | 20nm5
message_level | error
anlg_voltage | 1_0V
anlg_link | sr
support_mode | user_mode
protocol_mode | teng_baser_mode
pma_mode | basic
duplex_mode | duplex
channels | 1
set_data_rate | 10800
rcfg_iface_enable | 0
enable_simple_interface | 1
enable_split_interface | 0
set_enable_calibration | 1
enable_calibration | 1
set_disconnect_analog_resets | 0
enable_analog_resets | 1
enable_reset_sequence | 1
enable_transparent_pcs | 0
enable_parallel_loopback | 0
bonded_mode | not_bonded
set_pcs_bonding_master | Auto
pcs_bonding_master | 0
tx_pma_clk_div | 1
plls | 1
pll_select | 0
enable_port_tx_analog_reset_ack | 0
enable_port_tx_pma_clkout | 0
enable_port_tx_pma_div_clkout | 1
tx_pma_div_clkout_divider | 33
enable_port_tx_pma_iqtxrx_clkout | 0
enable_port_tx_pma_elecidle | 0
enable_port_tx_pma_qpipullup | 0
enable_port_tx_pma_qpipulldn | 0
enable_port_tx_pma_txdetectrx | 0
enable_port_tx_pma_rxfound | 0
enable_port_rx_seriallpbken_tx | 1
number_physical_bonding_clocks | 1
cdr_refclk_cnt | 1
cdr_refclk_select | 0
set_cdr_refclk_freq | 270.000000
rx_ppm_detect_threshold | 1000
rx_pma_ctle_adaptation_mode | manual
rx_pma_dfe_adaptation_mode | disabled
rx_pma_dfe_fixed_taps | 3
enable_ports_adaptation | 0
enable_port_rx_analog_reset_ack | 0
enable_port_rx_pma_clkout | 0
enable_port_rx_pma_div_clkout | 1
rx_pma_div_clkout_divider | 33
enable_port_rx_pma_iqtxrx_clkout | 0
enable_port_rx_pma_clkslip | 0
enable_port_rx_pma_qpipulldn | 0
enable_port_rx_is_lockedtodata | 1
enable_port_rx_is_lockedtoref | 1
enable_ports_rx_manual_cdr_mode | 0
enable_ports_rx_manual_ppm | 0
enable_port_rx_signaldetect | 0
enable_port_rx_seriallpbken | 1
enable_ports_rx_prbs | 0
std_pcs_pma_width | 10
display_std_tx_pld_pcs_width | 10
display_std_rx_pld_pcs_width | 10
std_low_latency_bypass_enable | 0
enable_hip | 0
enable_skp_ports | 0
enable_hard_reset | 0
set_hip_cal_en | 0
hip_cal_en | disable
enable_pcie_data_mask_option | 0
std_data_mask_count_multi | 0
std_tx_pcfifo_mode | low_latency
std_rx_pcfifo_mode | low_latency
enable_port_tx_std_pcfifo_full | 0
enable_port_tx_std_pcfifo_empty | 0
enable_port_rx_std_pcfifo_full | 0
enable_port_rx_std_pcfifo_empty | 0
std_tx_byte_ser_mode | Disabled
std_rx_byte_deser_mode | Disabled
std_tx_8b10b_enable | 0
std_tx_8b10b_disp_ctrl_enable | 0
std_rx_8b10b_enable | 0
std_rx_rmfifo_mode | disabled
std_rx_rmfifo_pattern_n | 0
std_rx_rmfifo_pattern_p | 0
enable_port_rx_std_rmfifo_full | 0
enable_port_rx_std_rmfifo_empty | 0
pcie_rate_match | Bypass
std_tx_bitslip_enable | 0
enable_port_tx_std_bitslipboundarysel | 0
std_rx_word_aligner_mode | bitslip
std_rx_word_aligner_pattern_len | 7
std_rx_word_aligner_pattern | 0
std_rx_word_aligner_rknumber | 3
std_rx_word_aligner_renumber | 3
std_rx_word_aligner_rgnumber | 3
std_rx_word_aligner_rvnumber | 0
std_rx_word_aligner_fast_sync_status_enable | 0
enable_port_rx_std_wa_patternalign | 0
enable_port_rx_std_wa_a1a2size | 0
enable_port_rx_std_bitslipboundarysel | 0
enable_port_rx_std_bitslip | 0
std_tx_bitrev_enable | 0
std_tx_byterev_enable | 0
std_tx_polinv_enable | 0
enable_port_tx_polinv | 0
std_rx_bitrev_enable | 0
enable_port_rx_std_bitrev_ena | 0
std_rx_byterev_enable | 0
enable_port_rx_std_byterev_ena | 0
std_rx_polinv_enable | 0
enable_port_rx_polinv | 0
enable_port_rx_std_signaldetect | 0
enable_ports_pipe_sw | 0
enable_ports_pipe_hclk | 0
enable_ports_pipe_g3_analog | 0
enable_ports_pipe_rx_elecidle | 0
enable_port_pipe_rx_polarity | 0
enh_pcs_pma_width | 64
enh_pld_pcs_width | 66
enh_low_latency_enable | 0
enh_rxtxfifo_double_width | 0
enh_txfifo_mode | Phase compensation
enh_txfifo_pfull | 11
enh_txfifo_pempty | 2
enable_port_tx_enh_fifo_full | 1
enable_port_tx_enh_fifo_pfull | 1
enable_port_tx_enh_fifo_empty | 1
enable_port_tx_enh_fifo_pempty | 1
enable_port_tx_enh_fifo_cnt | 0
enh_rxfifo_mode | 10GBase-R
enh_rxfifo_pfull | 23
enh_rxfifo_pempty | 2
enh_rxfifo_align_del | 0
enh_rxfifo_control_del | 0
enable_port_rx_enh_data_valid | 1
enable_port_rx_enh_fifo_full | 1
enable_port_rx_enh_fifo_pfull | 0
enable_port_rx_enh_fifo_empty | 1
enable_port_rx_enh_fifo_pempty | 0
enable_port_rx_enh_fifo_cnt | 0
enable_port_rx_enh_fifo_del | 0
enable_port_rx_enh_fifo_insert | 0
enable_port_rx_enh_fifo_rd_en | 0
enable_port_rx_enh_fifo_align_val | 0
enable_port_rx_enh_fifo_align_clr | 0
enh_tx_frmgen_enable | 0
enh_tx_frmgen_mfrm_length | 2048
enh_tx_frmgen_burst_enable | 0
enable_port_tx_enh_frame | 0
enable_port_tx_enh_frame_diag_status | 0
enable_port_tx_enh_frame_burst_en | 0
enh_rx_frmsync_enable | 0
enh_rx_frmsync_mfrm_length | 2048
enable_port_rx_enh_frame | 0
enable_port_rx_enh_frame_lock | 0
enable_port_rx_enh_frame_diag_status | 0
enh_tx_crcgen_enable | 0
enh_tx_crcerr_enable | 0
enh_rx_crcchk_enable | 0
enable_port_rx_enh_crc32_err | 0
enable_port_rx_enh_highber | 0
enable_port_rx_enh_highber_clr_cnt | 0
enable_port_rx_enh_clr_errblk_count | 0
enh_tx_64b66b_enable | 1
enh_rx_64b66b_enable | 1
enh_tx_sh_err | 0
enh_tx_scram_enable | 1
enh_tx_scram_seed | 288230376151711743
enh_rx_descram_enable | 1
enh_tx_dispgen_enable | 0
enh_rx_dispchk_enable | 0
enh_tx_randomdispbit_enable | 0
enh_rx_blksync_enable | 1
enable_port_rx_enh_blk_lock | 1
enh_tx_bitslip_enable | 0
enh_tx_polinv_enable | 0
enh_rx_bitslip_enable | 0
enh_rx_polinv_enable | 0
enable_port_tx_enh_bitslip | 0
enable_port_rx_enh_bitslip | 0
enh_rx_krfec_err_mark_enable | 0
enh_rx_krfec_err_mark_type | 10G
enh_tx_krfec_burst_err_enable | 0
enh_tx_krfec_burst_err_len | 1
enable_port_krfec_tx_enh_frame | 0
enable_port_krfec_rx_enh_frame | 0
enable_port_krfec_rx_enh_frame_diag_status | 0
pcs_direct_width | 8
generate_docs | 1
generate_add_hdl_instance_example | 0
validation_rule_select |
enable_advanced_options | 0
enable_physical_bonding_clocks | 0
enable_debug_options | 0
enable_advanced_avmm_options | 0
enable_odi_accelerator | 0
l_channels | 1
tx_enable | 1
datapath_select | Enhanced
rx_enable | 1
l_split_iface | 0
l_pcs_pma_width | 64
l_tx_pld_pcs_width | 66
l_rx_pld_pcs_width | 66
l_pll_settings | 337.500000 {refclk 337.500000 m 8 n 1 lpfd 2 lpd 1 fvco 5400.0} 675.000000 {refclk 675.000000 m 8 n 2 lpfd 2 lpd 1 fvco 5400.0} 300.000000 {refclk 300.000000 m 9 n 1 lpfd 2 lpd 1 fvco 5400.0} 600.000000 {refclk 600.000000 m 9 n 2 lpfd 2 lpd 1 fvco 5400.0} 270.000000 {refclk 270.000000 m 10 n 1 lpfd 2 lpd 1 fvco 5400.0} 540.000000 {refclk 540.000000 m 10 n 2 lpfd 2 lpd 1 fvco 5400.0} 245.454545 {refclk 245.454545 m 11 n 1 lpfd 2 lpd 1 fvco 5400.0} 490.909091 {refclk 490.909091 m 11 n 2 lpfd 2 lpd 1 fvco 5400.0} 225.000000 {refclk 225.000000 m 12 n 1 lpfd 2 lpd 1 fvco 5400.0} 450.000000 {refclk 450.000000 m 12 n 2 lpfd 2 lpd 1 fvco 5400.0} 207.692308 {refclk 207.692308 m 13 n 1 lpfd 2 lpd 1 fvco 5400.0} 415.384615 {refclk 415.384615 m 13 n 2 lpfd 2 lpd 1 fvco 5400.0} 192.857143 {refclk 192.857143 m 14 n 1 lpfd 2 lpd 1 fvco 5400.0} 385.714286 {refclk 385.714286 m 14 n 2 lpfd 2 lpd 1 fvco 5400.0} 771.428571 {refclk 771.428571 m 14 n 4 lpfd 2 lpd 1 fvco 5400.0} 180.000000 {refclk 180.000000 m 15 n 1 lpfd 2 lpd 1 fvco 5400.0} 360.000000 {refclk 360.000000 m 15 n 2 lpfd 2 lpd 1 fvco 5400.0} 720.000000 {refclk 720.000000 m 15 n 4 lpfd 2 lpd 1 fvco 5400.0} 168.750000 {refclk 168.750000 m 16 n 1 lpfd 2 lpd 1 fvco 5400.0} 158.823529 {refclk 158.823529 m 17 n 1 lpfd 2 lpd 1 fvco 5400.0} 317.647059 {refclk 317.647059 m 17 n 2 lpfd 2 lpd 1 fvco 5400.0} 635.294118 {refclk 635.294118 m 17 n 4 lpfd 2 lpd 1 fvco 5400.0} 150.000000 {refclk 150.000000 m 18 n 1 lpfd 2 lpd 1 fvco 5400.0} 142.105263 {refclk 142.105263 m 19 n 1 lpfd 2 lpd 1 fvco 5400.0} 284.210526 {refclk 284.210526 m 19 n 2 lpfd 2 lpd 1 fvco 5400.0} 568.421053 {refclk 568.421053 m 19 n 4 lpfd 2 lpd 1 fvco 5400.0} 135.000000 {refclk 135.000000 m 20 n 1 lpfd 2 lpd 1 fvco 5400.0} 128.571429 {refclk 128.571429 m 21 n 1 lpfd 2 lpd 1 fvco 5400.0} 257.142857 {refclk 257.142857 m 21 n 2 lpfd 2 lpd 1 fvco 5400.0} 514.285714 {refclk 514.285714 m 21 n 4 lpfd 2 lpd 1 fvco 5400.0} 122.727273 {refclk 122.727273 m 22 n 1 lpfd 2 lpd 1 fvco 5400.0} 117.391304 {refclk 117.391304 m 23 n 1 lpfd 2 lpd 1 fvco 5400.0} 234.782609 {refclk 234.782609 m 23 n 2 lpfd 2 lpd 1 fvco 5400.0} 469.565217 {refclk 469.565217 m 23 n 4 lpfd 2 lpd 1 fvco 5400.0} 112.500000 {refclk 112.500000 m 24 n 1 lpfd 2 lpd 1 fvco 5400.0} 108.000000 {refclk 108.000000 m 25 n 1 lpfd 2 lpd 1 fvco 5400.0} 216.000000 {refclk 216.000000 m 25 n 2 lpfd 2 lpd 1 fvco 5400.0} 432.000000 {refclk 432.000000 m 25 n 4 lpfd 2 lpd 1 fvco 5400.0} 103.846154 {refclk 103.846154 m 26 n 1 lpfd 2 lpd 1 fvco 5400.0} 100.000000 {refclk 100.000000 m 27 n 1 lpfd 2 lpd 1 fvco 5400.0} 200.000000 {refclk 200.000000 m 27 n 2 lpfd 2 lpd 1 fvco 5400.0} 400.000000 {refclk 400.000000 m 27 n 4 lpfd 2 lpd 1 fvco 5400.0} 800.000000 {refclk 800.000000 m 27 n 8 lpfd 2 lpd 1 fvco 5400.0} 96.428571 {refclk 96.428571 m 28 n 1 lpfd 2 lpd 1 fvco 5400.0} 93.103448 {refclk 93.103448 m 29 n 1 lpfd 2 lpd 1 fvco 5400.0} 186.206897 {refclk 186.206897 m 29 n 2 lpfd 2 lpd 1 fvco 5400.0} 372.413793 {refclk 372.413793 m 29 n 4 lpfd 2 lpd 1 fvco 5400.0} 744.827586 {refclk 744.827586 m 29 n 8 lpfd 2 lpd 1 fvco 5400.0} 90.000000 {refclk 90.000000 m 30 n 1 lpfd 2 lpd 1 fvco 5400.0} 87.096774 {refclk 87.096774 m 31 n 1 lpfd 2 lpd 1 fvco 5400.0} 174.193548 {refclk 174.193548 m 31 n 2 lpfd 2 lpd 1 fvco 5400.0} 348.387097 {refclk 348.387097 m 31 n 4 lpfd 2 lpd 1 fvco 5400.0} 696.774194 {refclk 696.774194 m 31 n 8 lpfd 2 lpd 1 fvco 5400.0} 84.375000 {refclk 84.375000 m 32 n 1 lpfd 2 lpd 1 fvco 5400.0} 81.818182 {refclk 81.818182 m 33 n 1 lpfd 2 lpd 1 fvco 5400.0} 163.636364 {refclk 163.636364 m 33 n 2 lpfd 2 lpd 1 fvco 5400.0} 327.272727 {refclk 327.272727 m 33 n 4 lpfd 2 lpd 1 fvco 5400.0} 654.545455 {refclk 654.545455 m 33 n 8 lpfd 2 lpd 1 fvco 5400.0} 79.411765 {refclk 79.411765 m 34 n 1 lpfd 2 lpd 1 fvco 5400.0} 77.142857 {refclk 77.142857 m 35 n 1 lpfd 2 lpd 1 fvco 5400.0} 154.285714 {refclk 154.285714 m 35 n 2 lpfd 2 lpd 1 fvco 5400.0} 308.571429 {refclk 308.571429 m 35 n 4 lpfd 2 lpd 1 fvco 5400.0} 617.142857 {refclk 617.142857 m 35 n 8 lpfd 2 lpd 1 fvco 5400.0} 75.000000 {refclk 75.000000 m 36 n 1 lpfd 2 lpd 1 fvco 5400.0} 72.972973 {refclk 72.972973 m 37 n 1 lpfd 2 lpd 1 fvco 5400.0} 145.945946 {refclk 145.945946 m 37 n 2 lpfd 2 lpd 1 fvco 5400.0} 291.891892 {refclk 291.891892 m 37 n 4 lpfd 2 lpd 1 fvco 5400.0} 583.783784 {refclk 583.783784 m 37 n 8 lpfd 2 lpd 1 fvco 5400.0} 71.052632 {refclk 71.052632 m 38 n 1 lpfd 2 lpd 1 fvco 5400.0} 69.230769 {refclk 69.230769 m 39 n 1 lpfd 2 lpd 1 fvco 5400.0} 138.461538 {refclk 138.461538 m 39 n 2 lpfd 2 lpd 1 fvco 5400.0} 276.923077 {refclk 276.923077 m 39 n 4 lpfd 2 lpd 1 fvco 5400.0} 553.846154 {refclk 553.846154 m 39 n 8 lpfd 2 lpd 1 fvco 5400.0} 67.500000 {refclk 67.500000 m 40 n 1 lpfd 2 lpd 1 fvco 5400.0} 65.853659 {refclk 65.853659 m 41 n 1 lpfd 2 lpd 1 fvco 5400.0} 131.707317 {refclk 131.707317 m 41 n 2 lpfd 2 lpd 1 fvco 5400.0} 263.414634 {refclk 263.414634 m 41 n 4 lpfd 2 lpd 1 fvco 5400.0} 526.829268 {refclk 526.829268 m 41 n 8 lpfd 2 lpd 1 fvco 5400.0} 64.285714 {refclk 64.285714 m 42 n 1 lpfd 2 lpd 1 fvco 5400.0} 62.790698 {refclk 62.790698 m 43 n 1 lpfd 2 lpd 1 fvco 5400.0} 125.581395 {refclk 125.581395 m 43 n 2 lpfd 2 lpd 1 fvco 5400.0} 251.162791 {refclk 251.162791 m 43 n 4 lpfd 2 lpd 1 fvco 5400.0} 502.325581 {refclk 502.325581 m 43 n 8 lpfd 2 lpd 1 fvco 5400.0} 61.363636 {refclk 61.363636 m 44 n 1 lpfd 2 lpd 1 fvco 5400.0} 60.000000 {refclk 60.000000 m 45 n 1 lpfd 2 lpd 1 fvco 5400.0} 120.000000 {refclk 120.000000 m 45 n 2 lpfd 2 lpd 1 fvco 5400.0} 240.000000 {refclk 240.000000 m 45 n 4 lpfd 2 lpd 1 fvco 5400.0} 480.000000 {refclk 480.000000 m 45 n 8 lpfd 2 lpd 1 fvco 5400.0} 58.695652 {refclk 58.695652 m 46 n 1 lpfd 2 lpd 1 fvco 5400.0} 57.446809 {refclk 57.446809 m 47 n 1 lpfd 2 lpd 1 fvco 5400.0} 114.893617 {refclk 114.893617 m 47 n 2 lpfd 2 lpd 1 fvco 5400.0} 229.787234 {refclk 229.787234 m 47 n 4 lpfd 2 lpd 1 fvco 5400.0} 459.574468 {refclk 459.574468 m 47 n 8 lpfd 2 lpd 1 fvco 5400.0} 56.250000 {refclk 56.250000 m 48 n 1 lpfd 2 lpd 1 fvco 5400.0} 55.102041 {refclk 55.102041 m 49 n 1 lpfd 2 lpd 1 fvco 5400.0} 110.204082 {refclk 110.204082 m 49 n 2 lpfd 2 lpd 1 fvco 5400.0} 220.408163 {refclk 220.408163 m 49 n 4 lpfd 2 lpd 1 fvco 5400.0} 440.816327 {refclk 440.816327 m 49 n 8 lpfd 2 lpd 1 fvco 5400.0} 54.000000 {refclk 54.000000 m 50 n 1 lpfd 2 lpd 1 fvco 5400.0} 52.941176 {refclk 52.941176 m 51 n 1 lpfd 2 lpd 1 fvco 5400.0} 105.882353 {refclk 105.882353 m 51 n 2 lpfd 2 lpd 1 fvco 5400.0} 211.764706 {refclk 211.764706 m 51 n 4 lpfd 2 lpd 1 fvco 5400.0} 423.529412 {refclk 423.529412 m 51 n 8 lpfd 2 lpd 1 fvco 5400.0} 51.923077 {refclk 51.923077 m 52 n 1 lpfd 2 lpd 1 fvco 5400.0} 50.943396 {refclk 50.943396 m 53 n 1 lpfd 2 lpd 1 fvco 5400.0} 101.886792 {refclk 101.886792 m 53 n 2 lpfd 2 lpd 1 fvco 5400.0} 203.773585 {refclk 203.773585 m 53 n 4 lpfd 2 lpd 1 fvco 5400.0} 407.547170 {refclk 407.547170 m 53 n 8 lpfd 2 lpd 1 fvco 5400.0} 50.000000 {refclk 50.000000 m 54 n 1 lpfd 2 lpd 1 fvco 5400.0} allowed_ranges {50.000000 50.943396 51.923077 52.941176 54.000000 55.102041 56.250000 57.446809 58.695652 60.000000 61.363636 62.790698 64.285714 65.853659 67.500000 69.230769 71.052632 72.972973 75.000000 77.142857 79.411765 81.818182 84.375000 87.096774 90.000000 93.103448 96.428571 100.000000 101.886792 103.846154 105.882353 108.000000 110.204082 112.500000 114.893617 117.391304 120.000000 122.727273 125.581395 128.571429 131.707317 135.000000 138.461538 142.105263 145.945946 150.000000 154.285714 158.823529 163.636364 168.750000 174.193548 180.000000 186.206897 192.857143 200.000000 203.773585 207.692308 211.764706 216.000000 220.408163 225.000000 229.787234 234.782609 240.000000 245.454545 251.162791 257.142857 263.414634 270.000000 276.923077 284.210526 291.891892 300.000000 308.571429 317.647059 327.272727 337.500000 348.387097 360.000000 372.413793 385.714286 400.000000 407.547170 415.384615 423.529412 432.000000 440.816327 450.000000 459.574468 469.565217 480.000000 490.909091 502.325581 514.285714 526.829268 540.000000 553.846154 568.421053 583.783784 600.000000 617.142857 635.294118 654.545455 675.000000 696.774194 720.000000 744.827586 771.428571 800.000000}
l_pll_settings_key | 270.000000
l_enable_pma_bonding | 0
l_enable_reve_support | 1
enable_std | 0
l_enable_std_pipe | 0
l_enable_tx_std | 0
l_enable_rx_std | 0
l_enable_tx_std_iface | 0
l_enable_rx_std_iface | 0
l_std_tx_word_count | 1
l_std_tx_word_width | 10
l_std_tx_field_width | 11
l_std_rx_word_count | 1
l_std_rx_word_width | 10
l_std_rx_field_width | 16
l_std_tx_pld_pcs_width | 10
l_std_rx_pld_pcs_width | 10
l_std_data_mask_count_multi | 0
enable_enh | 1
l_enable_tx_enh | 1
l_enable_rx_enh | 1
l_enable_tx_enh_iface | 1
l_enable_rx_enh_iface | 1
enable_pcs_dir | 0
l_enable_tx_pcs_dir | 0
l_enable_rx_pcs_dir | 0
l_rcfg_ifaces | 1
l_rcfg_addr_bits | 10
rcfg_enable | 1
rcfg_shared | 0
rcfg_jtag_enable | 1
rcfg_separate_avmm_busy | 0
rcfg_enable_avmm_busy_port | 0
adme_prot_mode | teng_baser_mode
adme_data_rate | 10800000000
enable_pcie_dfe_ip | false
sim_reduced_counters | false
disable_continuous_dfe | false
set_embedded_debug_enable | 0
set_capability_reg_enable | 1
set_user_identifier | 0
set_csr_soft_logic_enable | 1
set_prbs_soft_logic_enable | 1
set_odi_soft_logic_enable | 0
dbg_embedded_debug_enable | 1
dbg_capability_reg_enable | 1
dbg_user_identifier | 0
dbg_stat_soft_logic_enable | 1
dbg_ctrl_soft_logic_enable | 1
dbg_prbs_soft_logic_enable | 1
dbg_odi_soft_logic_enable | 0
rcfg_file_prefix | altera_xcvr_native_a10_11g
rcfg_sv_file_enable | 0
rcfg_h_file_enable | 0
rcfg_mif_file_enable | 1
rcfg_multi_enable | 0
set_rcfg_emb_strm_enable | 0
rcfg_emb_strm_enable | 0
rcfg_reduced_files_enable | 0
rcfg_profile_cnt | 2
rcfg_profile_select | 1
rcfg_profile_data0 |
rcfg_profile_data1 |
rcfg_profile_data2 |
rcfg_profile_data3 |
rcfg_profile_data4 |
rcfg_profile_data5 |
rcfg_profile_data6 |
rcfg_profile_data7 |
rcfg_params | anlg_voltage,anlg_link,support_mode,protocol_mode,pma_mode,duplex_mode,channels,set_data_rate,rcfg_iface_enable,enable_simple_interface,enable_split_interface,set_enable_calibration,enable_parallel_loopback,bonded_mode,set_pcs_bonding_master,tx_pma_clk_div,plls,pll_select,enable_port_tx_analog_reset_ack,enable_port_tx_pma_clkout,enable_port_tx_pma_div_clkout,tx_pma_div_clkout_divider,enable_port_tx_pma_iqtxrx_clkout,enable_port_tx_pma_elecidle,enable_port_tx_pma_qpipullup,enable_port_tx_pma_qpipulldn,enable_port_tx_pma_txdetectrx,enable_port_tx_pma_rxfound,enable_port_rx_seriallpbken_tx,number_physical_bonding_clocks,cdr_refclk_cnt,cdr_refclk_select,set_cdr_refclk_freq,rx_ppm_detect_threshold,rx_pma_ctle_adaptation_mode,rx_pma_dfe_adaptation_mode,rx_pma_dfe_fixed_taps,enable_ports_adaptation,enable_port_rx_analog_reset_ack,enable_port_rx_pma_clkout,enable_port_rx_pma_div_clkout,rx_pma_div_clkout_divider,enable_port_rx_pma_iqtxrx_clkout,enable_port_rx_pma_clkslip,enable_port_rx_pma_qpipulldn,enable_port_rx_is_lockedtodata,enable_port_rx_is_lockedtoref,enable_ports_rx_manual_cdr_mode,enable_ports_rx_manual_ppm,enable_port_rx_signaldetect,enable_port_rx_seriallpbken,enable_ports_rx_prbs,std_pcs_pma_width,std_low_latency_bypass_enable,enable_hip,enable_hard_reset,set_hip_cal_en,std_tx_pcfifo_mode,std_rx_pcfifo_mode,enable_port_tx_std_pcfifo_full,enable_port_tx_std_pcfifo_empty,enable_port_rx_std_pcfifo_full,enable_port_rx_std_pcfifo_empty,std_tx_byte_ser_mode,std_rx_byte_deser_mode,std_tx_8b10b_enable,std_tx_8b10b_disp_ctrl_enable,std_rx_8b10b_enable,std_rx_rmfifo_mode,std_rx_rmfifo_pattern_n,std_rx_rmfifo_pattern_p,enable_port_rx_std_rmfifo_full,enable_port_rx_std_rmfifo_empty,pcie_rate_match,std_tx_bitslip_enable,enable_port_tx_std_bitslipboundarysel,std_rx_word_aligner_mode,std_rx_word_aligner_pattern_len,std_rx_word_aligner_pattern,std_rx_word_aligner_rknumber,std_rx_word_aligner_renumber,std_rx_word_aligner_rgnumber,std_rx_word_aligner_fast_sync_status_enable,enable_port_rx_std_wa_patternalign,enable_port_rx_std_wa_a1a2size,enable_port_rx_std_bitslipboundarysel,enable_port_rx_std_bitslip,std_tx_bitrev_enable,std_tx_byterev_enable,std_tx_polinv_enable,enable_port_tx_polinv,std_rx_bitrev_enable,enable_port_rx_std_bitrev_ena,std_rx_byterev_enable,enable_port_rx_std_byterev_ena,std_rx_polinv_enable,enable_port_rx_polinv,enable_port_rx_std_signaldetect,enable_ports_pipe_sw,enable_ports_pipe_hclk,enable_ports_pipe_g3_analog,enable_ports_pipe_rx_elecidle,enable_port_pipe_rx_polarity,enh_pcs_pma_width,enh_pld_pcs_width,enh_low_latency_enable,enh_rxtxfifo_double_width,enh_txfifo_mode,enh_txfifo_pfull,enh_txfifo_pempty,enable_port_tx_enh_fifo_full,enable_port_tx_enh_fifo_pfull,enable_port_tx_enh_fifo_empty,enable_port_tx_enh_fifo_pempty,enable_port_tx_enh_fifo_cnt,enh_rxfifo_mode,enh_rxfifo_pfull,enh_rxfifo_pempty,enh_rxfifo_align_del,enh_rxfifo_control_del,enable_port_rx_enh_data_valid,enable_port_rx_enh_fifo_full,enable_port_rx_enh_fifo_pfull,enable_port_rx_enh_fifo_empty,enable_port_rx_enh_fifo_pempty,enable_port_rx_enh_fifo_cnt,enable_port_rx_enh_fifo_del,enable_port_rx_enh_fifo_insert,enable_port_rx_enh_fifo_rd_en,enable_port_rx_enh_fifo_align_val,enable_port_rx_enh_fifo_align_clr,enh_tx_frmgen_enable,enh_tx_frmgen_mfrm_length,enh_tx_frmgen_burst_enable,enable_port_tx_enh_frame,enable_port_tx_enh_frame_diag_status,enable_port_tx_enh_frame_burst_en,enh_rx_frmsync_enable,enh_rx_frmsync_mfrm_length,enable_port_rx_enh_frame,enable_port_rx_enh_frame_lock,enable_port_rx_enh_frame_diag_status,enh_tx_crcgen_enable,enh_tx_crcerr_enable,enh_rx_crcchk_enable,enable_port_rx_enh_crc32_err,enable_port_rx_enh_highber,enable_port_rx_enh_highber_clr_cnt,enable_port_rx_enh_clr_errblk_count,enh_tx_64b66b_enable,enh_rx_64b66b_enable,enh_tx_sh_err,enh_tx_scram_enable,enh_tx_scram_seed,enh_rx_descram_enable,enh_tx_dispgen_enable,enh_rx_dispchk_enable,enh_tx_randomdispbit_enable,enh_rx_blksync_enable,enable_port_rx_enh_blk_lock,enh_tx_bitslip_enable,enh_tx_polinv_enable,enh_rx_bitslip_enable,enh_rx_polinv_enable,enable_port_tx_enh_bitslip,enable_port_rx_enh_bitslip,enh_rx_krfec_err_mark_enable,enh_rx_krfec_err_mark_type,enh_tx_krfec_burst_err_enable,enh_tx_krfec_burst_err_len,enable_port_krfec_tx_enh_frame,enable_port_krfec_rx_enh_frame,enable_port_krfec_rx_enh_frame_diag_status,pcs_direct_width,enable_analog_settings,anlg_tx_analog_mode,anlg_enable_tx_default_ovr,anlg_tx_vod_output_swing_ctrl,anlg_tx_pre_emp_sign_pre_tap_1t,anlg_tx_pre_emp_switching_ctrl_pre_tap_1t,anlg_tx_pre_emp_sign_pre_tap_2t,anlg_tx_pre_emp_switching_ctrl_pre_tap_2t,anlg_tx_pre_emp_sign_1st_post_tap,anlg_tx_pre_emp_switching_ctrl_1st_post_tap,anlg_tx_pre_emp_sign_2nd_post_tap,anlg_tx_pre_emp_switching_ctrl_2nd_post_tap,anlg_tx_slew_rate_ctrl,anlg_tx_compensation_en,anlg_tx_term_sel,anlg_enable_rx_default_ovr,anlg_rx_one_stage_enable,anlg_rx_eq_dc_gain_trim,anlg_rx_adp_ctle_acgain_4s,anlg_rx_adp_ctle_eqz_1s_sel,anlg_rx_adp_vga_sel,anlg_rx_adp_dfe_fxtap1,anlg_rx_adp_dfe_fxtap2,anlg_rx_adp_dfe_fxtap3,anlg_rx_adp_dfe_fxtap4,anlg_rx_adp_dfe_fxtap5,anlg_rx_adp_dfe_fxtap6,anlg_rx_adp_dfe_fxtap7,anlg_rx_adp_dfe_fxtap8,anlg_rx_adp_dfe_fxtap9,anlg_rx_adp_dfe_fxtap10,anlg_rx_adp_dfe_fxtap11,anlg_rx_term_sel
rcfg_param_labels | VCCR_GXB and VCCT_GXB supply voltage for the Transceiver,Tranceiver Link Type,Protocol support mode,Transceiver configuration rules,PMA configuration rules,Transceiver mode,Number of data channels,Data rate,Enable datapath and interface reconfiguration,Enable simplified data interface,Provide separate interface for each channel,Enable calibration,Enable parallel loopback,TX channel bonding mode,PCS TX channel bonding master,TX local clock division factor,Number of TX PLL clock inputs per channel,Initial TX PLL clock input selection,Enable tx_analog_reset_ack port,Enable tx_pma_clkout port,Enable tx_pma_div_clkout port,tx_pma_div_clkout division factor,Enable tx_pma_iqtxrx_clkout port,Enable tx_pma_elecidle port,Enable tx_pma_qpipullup port (QPI),Enable tx_pma_qpipulldn port (QPI),Enable tx_pma_txdetectrx port (QPI),Enable tx_pma_rxfound port (QPI),Enable rx_seriallpbken port,Number of physical bonding clock ports to use.,Number of CDR reference clocks,Selected CDR reference clock,Selected CDR reference clock frequency,PPM detector threshold,CTLE mode,DFE mode,Number of fixed dfe taps,Enable adaptation control ports,Enable rx_analog_reset_ack port,Enable rx_pma_clkout port,Enable rx_pma_div_clkout port,rx_pma_div_clkout division factor,Enable rx_pma_iqtxrx_clkout port,Enable rx_pma_clkslip port,Enable rx_pma_qpipulldn port (QPI),Enable rx_is_lockedtodata port,Enable rx_is_lockedtoref port,Enable rx_set_locktodata and rx_set_locktoref ports,Enable rx_fref and rx_clklow ports,Enable rx_signaldetect port,Enable rx_seriallpbken port,Enable PRBS verifier control and status ports,Standard PCS / PMA interface width,Enable 'Standard PCS' low latency mode,Enable PCIe hard IP support,Enable hard reset controller (HIP),Enable PCIe hard IP calibration,TX FIFO mode,RX FIFO mode,Enable tx_std_pcfifo_full port,Enable tx_std_pcfifo_empty port,Enable rx_std_pcfifo_full port,Enable rx_std_pcfifo_empty port,TX byte serializer mode,RX byte deserializer mode,Enable TX 8B/10B encoder,Enable TX 8B/10B disparity control,Enable RX 8B/10B decoder,RX rate match FIFO mode,RX rate match insert/delete -ve pattern (hex),RX rate match insert/delete +ve pattern (hex),Enable rx_std_rmfifo_full port,Enable rx_std_rmfifo_empty port,PCI Express Gen 3 rate match FIFO mode,Enable TX bitslip,Enable tx_std_bitslipboundarysel port,RX word aligner mode,RX word aligner pattern length,RX word aligner pattern (hex),Number of word alignment patterns to achieve sync,Number of invalid data words to lose sync,Number of valid data words to decrement error count,Enable fast sync status reporting for deterministic latency SM,Enable rx_std_wa_patternalign port,Enable rx_std_wa_a1a2size port,Enable rx_std_bitslipboundarysel port,Enable rx_bitslip port,Enable TX bit reversal,Enable TX byte reversal,Enable TX polarity inversion,Enable tx_polinv port,Enable RX bit reversal,Enable rx_std_bitrev_ena port,Enable RX byte reversal,Enable rx_std_byterev_ena port,Enable RX polarity inversion,Enable rx_polinv port,Enable rx_std_signaldetect port,Enable PCIe dynamic datarate switch ports,Enable PCIe pipe_hclk_in and pipe_hclk_out ports,Enable PCIe Gen 3 analog control ports,Enable PCIe electrical idle control and status ports,Enable PCIe pipe_rx_polarity port,Enhanced PCS / PMA interface width,FPGA fabric / Enhanced PCS interface width,Enable 'Enhanced PCS' low latency mode,Enable RX/TX FIFO double width mode,TX FIFO mode,TX FIFO partially full threshold,TX FIFO partially empty threshold,Enable tx_enh_fifo_full port,Enable tx_enh_fifo_pfull port,Enable tx_enh_fifo_empty port,Enable tx_enh_fifo_pempty port,Enable tx_enh_fifo_cnt port,RX FIFO mode,RX FIFO partially full threshold,RX FIFO partially empty threshold,Enable RX FIFO alignment word deletion (Interlaken),Enable RX FIFO control word deletion (Interlaken),Enable rx_enh_data_valid port,Enable rx_enh_fifo_full port,Enable rx_enh_fifo_pfull port,Enable rx_enh_fifo_empty port,Enable rx_enh_fifo_pempty port,Enable rx_enh_fifo_cnt port,Enable rx_enh_fifo_del port (10GBASE-R),Enable rx_enh_fifo_insert port (10GBASE-R),Enable rx_enh_fifo_rd_en port,Enable rx_enh_fifo_align_val port (Interlaken),Enable rx_enh_fifo_align_clr port (Interlaken),Enable Interlaken frame generator,Frame generator metaframe length,Enable frame generator burst control,Enable tx_enh_frame port,Enable tx_enh_frame_diag_status port,Enable tx_enh_frame_burst_en port,Enable Interlaken frame synchronizer,Frame synchronizer metaframe length,Enable rx_enh_frame port,Enable rx_enh_frame_lock port,Enable rx_enh_frame_diag_status port,Enable Interlaken TX CRC-32 generator,Enable Interlaken TX CRC-32 generator error insertion,Enable Interlaken RX CRC-32 checker,Enable rx_enh_crc32_err port,Enable rx_enh_highber port (10GBASE-R),Enable rx_enh_highber_clr_cnt port (10GBASE-R),Enable rx_enh_clr_errblk_count port (10GBASE-R & FEC),Enable TX 64b/66b encoder,Enable RX 64b/66b decoder,Enable TX sync header error insertion,Enable TX scrambler (10GBASE-R/Interlaken),TX scrambler seed (10GBASE-R/Interlaken),Enable RX descrambler (10GBASE-R/Interlaken),Enable Interlaken TX disparity generator,Enable Interlaken RX disparity checker,Enable Interlaken TX random disparity bit,Enable RX block synchronizer,Enable rx_enh_blk_lock port,Enable TX data bitslip,Enable TX data polarity inversion,Enable RX data bitslip,Enable RX data polarity inversion,Enable tx_enh_bitslip port,Enable rx_bitslip port,Enable RX KR-FEC error marking,Error marking type,Enable KR-FEC TX error insertion,KR-FEC TX error insertion spacing,Enable tx_enh_frame port,Enable rx_enh_frame port,Enable rx_enh_frame_diag_status port,PCS Direct interface width,Include PMA analog settings in configuration files,Analog Mode (Altera-recommended Default Setting Rules),Override Altera-recommended Analog Mode Default Settings,Output Swing Level (VOD),Pre-Emphasis First Pre-Tap Polarity,Pre-Emphasis First Pre-Tap Magnitude,Pre-Emphasis Second Pre-Tap Polarity,Pre-Emphasis Second Pre-Tap Magnitude,Pre-Emphasis First Post-Tap Polarity,Pre-Emphasis First Post-Tap Magnitude,Pre-Emphasis Second Post-Tap Polarity,Pre-Emphasis Second Post-Tap Magnitude,Slew Rate Control,High-Speed Compensation,On-Chip Termination,Override Altera-recommended Default Settings,CTLE (Continuous Time Linear Equalizer) mode,DC Gain Control of High Gain Mode CTLE,AC Gain Control of High Gain Mode CTLE,AC Gain Control of High Data Rate Mode CTLE,Variable Gain Amplifier (VGA) Voltage Swing Select,Decision Feedback Equalizer (DFE) Fixed Tap 1 Co-efficient,Decision Feedback Equalizer (DFE) Fixed Tap 2 Co-efficient,Decision Feedback Equalizer (DFE) Fixed Tap 3 Co-efficient,Decision Feedback Equalizer (DFE) Fixed Tap 4 Co-efficient,Decision Feedback Equalizer (DFE) Fixed Tap 5 Co-efficient,Decision Feedback Equalizer (DFE) Fixed Tap 6 Co-efficient,Decision Feedback Equalizer (DFE) Fixed Tap 7 Co-efficient,Decision Feedback Equalizer (DFE) Fixed Tap 8 Co-efficient,Decision Feedback Equalizer (DFE) Fixed Tap 9 Co-efficient,Decision Feedback Equalizer (DFE) Fixed Tap 10 Co-efficient,Decision Feedback Equalizer (DFE) Fixed Tap 11 Co-efficient,On-Chip Termination
rcfg_param_vals0 |
rcfg_param_vals1 |
rcfg_param_vals2 |
rcfg_param_vals3 |
rcfg_param_vals4 |
rcfg_param_vals5 |
rcfg_param_vals6 |
rcfg_param_vals7 |
l_rcfg_datapath_message | 0
enable_analog_settings | 0
anlg_tx_analog_mode | user_custom
anlg_enable_tx_default_ovr | 0
anlg_tx_vod_output_swing_ctrl | 0
anlg_tx_pre_emp_sign_pre_tap_1t | fir_pre_1t_neg
anlg_tx_pre_emp_switching_ctrl_pre_tap_1t | 0
anlg_tx_pre_emp_sign_pre_tap_2t | fir_pre_2t_neg
anlg_tx_pre_emp_switching_ctrl_pre_tap_2t | 0
anlg_tx_pre_emp_sign_1st_post_tap | fir_post_1t_neg
anlg_tx_pre_emp_switching_ctrl_1st_post_tap | 0
anlg_tx_pre_emp_sign_2nd_post_tap | fir_post_2t_neg
anlg_tx_pre_emp_switching_ctrl_2nd_post_tap | 0
anlg_tx_slew_rate_ctrl | slew_r7
anlg_tx_compensation_en | enable
anlg_tx_term_sel | r_r1
anlg_enable_rx_default_ovr | 0
anlg_rx_one_stage_enable | s1_mode
anlg_rx_eq_dc_gain_trim | stg2_gain7
anlg_rx_adp_ctle_acgain_4s | radp_ctle_acgain_4s_1
anlg_rx_adp_ctle_eqz_1s_sel | radp_ctle_eqz_1s_sel_3
anlg_rx_adp_vga_sel | radp_vga_sel_2
anlg_rx_adp_dfe_fxtap1 | radp_dfe_fxtap1_0
anlg_rx_adp_dfe_fxtap2 | radp_dfe_fxtap2_0
anlg_rx_adp_dfe_fxtap3 | radp_dfe_fxtap3_0
anlg_rx_adp_dfe_fxtap4 | radp_dfe_fxtap4_0
anlg_rx_adp_dfe_fxtap5 | radp_dfe_fxtap5_0
anlg_rx_adp_dfe_fxtap6 | radp_dfe_fxtap6_0
anlg_rx_adp_dfe_fxtap7 | radp_dfe_fxtap7_0
anlg_rx_adp_dfe_fxtap8 | radp_dfe_fxtap8_0
anlg_rx_adp_dfe_fxtap9 | radp_dfe_fxtap9_0
anlg_rx_adp_dfe_fxtap10 | radp_dfe_fxtap10_0
anlg_rx_adp_dfe_fxtap11 | radp_dfe_fxtap11_0
anlg_rx_term_sel | r_r1
l_anlg_tx_enable | 0
l_anlg_rx_enable | 0
hssi_gen3_rx_pcs_block_sync | bypass_block_sync
hssi_gen3_rx_pcs_block_sync_sm | disable_blk_sync_sm
hssi_gen3_rx_pcs_cdr_ctrl_force_unalgn | disable
hssi_gen3_rx_pcs_lpbk_force | lpbk_frce_dis
hssi_gen3_rx_pcs_mode | disable_pcs
hssi_gen3_rx_pcs_rate_match_fifo | bypass_rm_fifo
hssi_gen3_rx_pcs_rate_match_fifo_latency | low_latency
hssi_gen3_rx_pcs_reverse_lpbk | rev_lpbk_dis
hssi_gen3_rx_pcs_rx_b4gb_par_lpbk | b4gb_par_lpbk_dis
hssi_gen3_rx_pcs_rx_force_balign | dis_force_balign
hssi_gen3_rx_pcs_rx_ins_del_one_skip | ins_del_one_skip_dis
hssi_gen3_rx_pcs_rx_num_fixed_pat | 0
hssi_gen3_rx_pcs_rx_test_out_sel | rx_test_out0
hssi_gen3_rx_pcs_sup_mode | user_mode
hssi_gen3_rx_pcs_silicon_rev | 20nm5es
hssi_gen3_rx_pcs_reconfig_settings | {}
hssi_gen3_tx_pcs_mode | disable_pcs
hssi_gen3_tx_pcs_reverse_lpbk | rev_lpbk_dis
hssi_gen3_tx_pcs_sup_mode | user_mode
hssi_gen3_tx_pcs_tx_bitslip | 0
hssi_gen3_tx_pcs_tx_gbox_byp | bypass_gbox
hssi_gen3_tx_pcs_silicon_rev | 20nm5es
hssi_krfec_rx_pcs_blksync_cor_en | detect
hssi_krfec_rx_pcs_bypass_gb | bypass_dis
hssi_krfec_rx_pcs_clr_ctrl | both_enabled
hssi_krfec_rx_pcs_ctrl_bit_reverse | ctrl_bit_reverse_en
hssi_krfec_rx_pcs_data_bit_reverse | data_bit_reverse_dis
hssi_krfec_rx_pcs_dv_start | with_blklock
hssi_krfec_rx_pcs_err_mark_type | err_mark_10g
hssi_krfec_rx_pcs_error_marking_en | err_mark_dis
hssi_krfec_rx_pcs_low_latency_en | disable
hssi_krfec_rx_pcs_lpbk_mode | lpbk_dis
hssi_krfec_rx_pcs_parity_invalid_enum | 8
hssi_krfec_rx_pcs_parity_valid_num | 4
hssi_krfec_rx_pcs_pipeln_blksync | enable
hssi_krfec_rx_pcs_pipeln_descrm | disable
hssi_krfec_rx_pcs_pipeln_errcorrect | disable
hssi_krfec_rx_pcs_pipeln_errtrap_ind | enable
hssi_krfec_rx_pcs_pipeln_errtrap_lfsr | disable
hssi_krfec_rx_pcs_pipeln_errtrap_loc | disable
hssi_krfec_rx_pcs_pipeln_errtrap_pat | disable
hssi_krfec_rx_pcs_pipeln_gearbox | enable
hssi_krfec_rx_pcs_pipeln_syndrm | enable
hssi_krfec_rx_pcs_pipeln_trans_dec | disable
hssi_krfec_rx_pcs_prot_mode | disable_mode
hssi_krfec_rx_pcs_receive_order | receive_lsb
hssi_krfec_rx_pcs_rx_testbus_sel | overall
hssi_krfec_rx_pcs_signal_ok_en | sig_ok_en
hssi_krfec_rx_pcs_sup_mode | user_mode
hssi_krfec_rx_pcs_silicon_rev | 20nm5es
hssi_krfec_rx_pcs_reconfig_settings | {}
hssi_krfec_tx_pcs_burst_err | burst_err_dis
hssi_krfec_tx_pcs_burst_err_len | burst_err_len1
hssi_krfec_tx_pcs_ctrl_bit_reverse | ctrl_bit_reverse_en
hssi_krfec_tx_pcs_data_bit_reverse | data_bit_reverse_dis
hssi_krfec_tx_pcs_enc_frame_query | enc_query_dis
hssi_krfec_tx_pcs_low_latency_en | disable
hssi_krfec_tx_pcs_pipeln_encoder | enable
hssi_krfec_tx_pcs_pipeln_scrambler | enable
hssi_krfec_tx_pcs_prot_mode | disable_mode
hssi_krfec_tx_pcs_sup_mode | user_mode
hssi_krfec_tx_pcs_transcode_err | trans_err_dis
hssi_krfec_tx_pcs_transmit_order | transmit_lsb
hssi_krfec_tx_pcs_tx_testbus_sel | overall
hssi_krfec_tx_pcs_silicon_rev | 20nm5es
hssi_10g_rx_pcs_align_del | align_del_dis
hssi_10g_rx_pcs_ber_bit_err_total_cnt | bit_err_total_cnt_10g
hssi_10g_rx_pcs_ber_clken | ber_clk_en
hssi_10g_rx_pcs_ber_xus_timer_window | 19530
hssi_10g_rx_pcs_bitslip_mode | bitslip_dis
hssi_10g_rx_pcs_blksync_bitslip_type | bitslip_comb
hssi_10g_rx_pcs_blksync_bitslip_wait_cnt | 1
hssi_10g_rx_pcs_blksync_bitslip_wait_type | bitslip_cnt
hssi_10g_rx_pcs_blksync_bypass | blksync_bypass_dis
hssi_10g_rx_pcs_blksync_clken | blksync_clk_en
hssi_10g_rx_pcs_blksync_enum_invalid_sh_cnt | enum_invalid_sh_cnt_10g
hssi_10g_rx_pcs_blksync_knum_sh_cnt_postlock | knum_sh_cnt_postlock_10g
hssi_10g_rx_pcs_blksync_knum_sh_cnt_prelock | knum_sh_cnt_prelock_10g
hssi_10g_rx_pcs_blksync_pipeln | blksync_pipeln_dis
hssi_10g_rx_pcs_clr_errblk_cnt_en | enable
hssi_10g_rx_pcs_control_del | control_del_none
hssi_10g_rx_pcs_crcchk_bypass | crcchk_bypass_en
hssi_10g_rx_pcs_crcchk_clken | crcchk_clk_dis
hssi_10g_rx_pcs_crcchk_inv | crcchk_inv_en
hssi_10g_rx_pcs_crcchk_pipeln | crcchk_pipeln_en
hssi_10g_rx_pcs_crcflag_pipeln | crcflag_pipeln_en
hssi_10g_rx_pcs_ctrl_bit_reverse | ctrl_bit_reverse_en
hssi_10g_rx_pcs_data_bit_reverse | data_bit_reverse_dis
hssi_10g_rx_pcs_dec_64b66b_rxsm_bypass | dec_64b66b_rxsm_bypass_dis
hssi_10g_rx_pcs_dec64b66b_clken | dec64b66b_clk_en
hssi_10g_rx_pcs_descrm_bypass | descrm_bypass_dis
hssi_10g_rx_pcs_descrm_clken | descrm_clk_en
hssi_10g_rx_pcs_descrm_mode | async
hssi_10g_rx_pcs_descrm_pipeln | enable
hssi_10g_rx_pcs_dft_clk_out_sel | rx_master_clk
hssi_10g_rx_pcs_dis_signal_ok | dis_signal_ok_en
hssi_10g_rx_pcs_dispchk_bypass | dispchk_bypass_en
hssi_10g_rx_pcs_empty_flag_type | empty_rd_side
hssi_10g_rx_pcs_fast_path | fast_path_dis
hssi_10g_rx_pcs_fec_clken | fec_clk_dis
hssi_10g_rx_pcs_fec_enable | fec_dis
hssi_10g_rx_pcs_fifo_double_read | fifo_double_read_dis
hssi_10g_rx_pcs_fifo_stop_rd | n_rd_empty
hssi_10g_rx_pcs_fifo_stop_wr | n_wr_full
hssi_10g_rx_pcs_force_align | force_align_dis
hssi_10g_rx_pcs_frmsync_bypass | frmsync_bypass_en
hssi_10g_rx_pcs_frmsync_clken | frmsync_clk_dis
hssi_10g_rx_pcs_frmsync_enum_scrm | enum_scrm_default
hssi_10g_rx_pcs_frmsync_enum_sync | enum_sync_default
hssi_10g_rx_pcs_frmsync_flag_type | location_only
hssi_10g_rx_pcs_frmsync_knum_sync | knum_sync_default
hssi_10g_rx_pcs_frmsync_mfrm_length | 2048
hssi_10g_rx_pcs_frmsync_pipeln | frmsync_pipeln_en
hssi_10g_rx_pcs_full_flag_type | full_wr_side
hssi_10g_rx_pcs_gb_rx_idwidth | width_64
hssi_10g_rx_pcs_gb_rx_odwidth | width_66
hssi_10g_rx_pcs_gbexp_clken | gbexp_clk_en
hssi_10g_rx_pcs_low_latency_en | disable
hssi_10g_rx_pcs_lpbk_mode | lpbk_dis
hssi_10g_rx_pcs_master_clk_sel | master_rx_pma_clk
hssi_10g_rx_pcs_pempty_flag_type | pempty_rd_side
hssi_10g_rx_pcs_pfull_flag_type | pfull_wr_side
hssi_10g_rx_pcs_phcomp_rd_del | phcomp_rd_del2
hssi_10g_rx_pcs_pld_if_type | fifo
hssi_10g_rx_pcs_prot_mode | teng_baser_mode
hssi_10g_rx_pcs_rand_clken | rand_clk_en
hssi_10g_rx_pcs_rd_clk_sel | rd_rx_pld_clk
hssi_10g_rx_pcs_rdfifo_clken | rdfifo_clk_en
hssi_10g_rx_pcs_rx_fifo_write_ctrl | blklock_stops
hssi_10g_rx_pcs_rx_scrm_width | bit64
hssi_10g_rx_pcs_rx_sh_location | lsb
hssi_10g_rx_pcs_rx_signal_ok_sel | synchronized_ver
hssi_10g_rx_pcs_rx_sm_bypass | rx_sm_bypass_dis
hssi_10g_rx_pcs_rx_sm_hiber | rx_sm_hiber_en
hssi_10g_rx_pcs_rx_sm_pipeln | rx_sm_pipeln_en
hssi_10g_rx_pcs_rx_testbus_sel | rx_fifo_testbus1
hssi_10g_rx_pcs_rx_true_b2b | b2b
hssi_10g_rx_pcs_rxfifo_empty | empty_default
hssi_10g_rx_pcs_rxfifo_full | full_default
hssi_10g_rx_pcs_rxfifo_mode | clk_comp_10g
hssi_10g_rx_pcs_rxfifo_pempty | 2
hssi_10g_rx_pcs_rxfifo_pfull | 23
hssi_10g_rx_pcs_stretch_num_stages | one_stage
hssi_10g_rx_pcs_sup_mode | user_mode
hssi_10g_rx_pcs_test_mode | test_off
hssi_10g_rx_pcs_wrfifo_clken | wrfifo_clk_en
hssi_10g_rx_pcs_advanced_user_mode | disable
hssi_10g_rx_pcs_silicon_rev | 20nm5es
hssi_10g_rx_pcs_reconfig_settings | {}
hssi_10g_tx_pcs_bitslip_en | bitslip_dis
hssi_10g_tx_pcs_bonding_dft_en | dft_dis
hssi_10g_tx_pcs_bonding_dft_val | dft_0
hssi_10g_tx_pcs_comp_cnt | 0
hssi_10g_tx_pcs_compin_sel | compin_master
hssi_10g_tx_pcs_crcgen_bypass | crcgen_bypass_en
hssi_10g_tx_pcs_crcgen_clken | crcgen_clk_dis
hssi_10g_tx_pcs_crcgen_err | crcgen_err_dis
hssi_10g_tx_pcs_crcgen_inv | crcgen_inv_en
hssi_10g_tx_pcs_ctrl_bit_reverse | ctrl_bit_reverse_en
hssi_10g_tx_pcs_ctrl_plane_bonding | individual
hssi_10g_tx_pcs_data_bit_reverse | data_bit_reverse_dis
hssi_10g_tx_pcs_dft_clk_out_sel | tx_master_clk
hssi_10g_tx_pcs_dispgen_bypass | dispgen_bypass_en
hssi_10g_tx_pcs_dispgen_clken | dispgen_clk_dis
hssi_10g_tx_pcs_dispgen_err | dispgen_err_dis
hssi_10g_tx_pcs_dispgen_pipeln | dispgen_pipeln_dis
hssi_10g_tx_pcs_distdwn_bypass_pipeln | distdwn_bypass_pipeln_dis
hssi_10g_tx_pcs_distdwn_master | distdwn_master_en
hssi_10g_tx_pcs_distup_bypass_pipeln | distup_bypass_pipeln_dis
hssi_10g_tx_pcs_distup_master | distup_master_en
hssi_10g_tx_pcs_dv_bond | dv_bond_dis
hssi_10g_tx_pcs_empty_flag_type | empty_rd_side
hssi_10g_tx_pcs_enc_64b66b_txsm_bypass | enc_64b66b_txsm_bypass_dis
hssi_10g_tx_pcs_enc64b66b_txsm_clken | enc64b66b_txsm_clk_en
hssi_10g_tx_pcs_fastpath | fastpath_dis
hssi_10g_tx_pcs_fec_clken | fec_clk_dis
hssi_10g_tx_pcs_fec_enable | fec_dis
hssi_10g_tx_pcs_fifo_double_write | fifo_double_write_dis
hssi_10g_tx_pcs_fifo_reg_fast | fifo_reg_fast_dis
hssi_10g_tx_pcs_fifo_stop_rd | rd_empty
hssi_10g_tx_pcs_fifo_stop_wr | n_wr_full
hssi_10g_tx_pcs_frmgen_burst | frmgen_burst_dis
hssi_10g_tx_pcs_frmgen_bypass | frmgen_bypass_en
hssi_10g_tx_pcs_frmgen_clken | frmgen_clk_dis
hssi_10g_tx_pcs_frmgen_mfrm_length | 2048
hssi_10g_tx_pcs_frmgen_pipeln | frmgen_pipeln_en
hssi_10g_tx_pcs_frmgen_pyld_ins | frmgen_pyld_ins_dis
hssi_10g_tx_pcs_frmgen_wordslip | frmgen_wordslip_dis
hssi_10g_tx_pcs_full_flag_type | full_wr_side
hssi_10g_tx_pcs_gb_pipeln_bypass | disable
hssi_10g_tx_pcs_gb_tx_idwidth | width_66
hssi_10g_tx_pcs_gb_tx_odwidth | width_64
hssi_10g_tx_pcs_gbred_clken | gbred_clk_en
hssi_10g_tx_pcs_indv | indv_en
hssi_10g_tx_pcs_low_latency_en | disable
hssi_10g_tx_pcs_master_clk_sel | master_tx_pma_clk
hssi_10g_tx_pcs_pempty_flag_type | pempty_rd_side
hssi_10g_tx_pcs_pfull_flag_type | pfull_wr_side
hssi_10g_tx_pcs_phcomp_rd_del | phcomp_rd_del4
hssi_10g_tx_pcs_pld_if_type | fifo
hssi_10g_tx_pcs_prot_mode | teng_baser_mode
hssi_10g_tx_pcs_pseudo_random | all_0
hssi_10g_tx_pcs_pseudo_seed_a | 288230376151711743
hssi_10g_tx_pcs_pseudo_seed_b | 288230376151711743
hssi_10g_tx_pcs_random_disp | disable
hssi_10g_tx_pcs_rdfifo_clken | rdfifo_clk_en
hssi_10g_tx_pcs_scrm_bypass | scrm_bypass_dis
hssi_10g_tx_pcs_scrm_clken | scrm_clk_en
hssi_10g_tx_pcs_scrm_mode | async
hssi_10g_tx_pcs_scrm_pipeln | enable
hssi_10g_tx_pcs_sh_err | sh_err_dis
hssi_10g_tx_pcs_sop_mark | sop_mark_dis
hssi_10g_tx_pcs_stretch_num_stages | one_stage
hssi_10g_tx_pcs_sup_mode | user_mode
hssi_10g_tx_pcs_test_mode | test_off
hssi_10g_tx_pcs_tx_scrm_err | scrm_err_dis
hssi_10g_tx_pcs_tx_scrm_width | bit64
hssi_10g_tx_pcs_tx_sh_location | lsb
hssi_10g_tx_pcs_tx_sm_bypass | tx_sm_bypass_dis
hssi_10g_tx_pcs_tx_sm_pipeln | tx_sm_pipeln_en
hssi_10g_tx_pcs_tx_testbus_sel | tx_fifo_testbus1
hssi_10g_tx_pcs_txfifo_empty | empty_default
hssi_10g_tx_pcs_txfifo_full | full_default
hssi_10g_tx_pcs_txfifo_mode | phase_comp
hssi_10g_tx_pcs_txfifo_pempty | 2
hssi_10g_tx_pcs_txfifo_pfull | 11
hssi_10g_tx_pcs_wr_clk_sel | wr_tx_pld_clk
hssi_10g_tx_pcs_wrfifo_clken | wrfifo_clk_en
hssi_10g_tx_pcs_advanced_user_mode | disable
hssi_10g_tx_pcs_silicon_rev | 20nm5es
hssi_10g_tx_pcs_reconfig_settings | {}
hssi_8g_rx_pcs_auto_error_replacement | dis_err_replace
hssi_8g_rx_pcs_auto_speed_nego | dis_asn
hssi_8g_rx_pcs_bit_reversal | dis_bit_reversal
hssi_8g_rx_pcs_bonding_dft_en | dft_dis
hssi_8g_rx_pcs_bonding_dft_val | dft_0
hssi_8g_rx_pcs_bypass_pipeline_reg | dis_bypass_pipeline
hssi_8g_rx_pcs_byte_deserializer | dis_bds
hssi_8g_rx_pcs_cdr_ctrl_rxvalid_mask | dis_rxvalid_mask
hssi_8g_rx_pcs_clkcmp_pattern_n | 0
hssi_8g_rx_pcs_clkcmp_pattern_p | 0
hssi_8g_rx_pcs_clock_gate_bds_dec_asn | en_bds_dec_asn_clk_gating
hssi_8g_rx_pcs_clock_gate_cdr_eidle | en_cdr_eidle_clk_gating
hssi_8g_rx_pcs_clock_gate_dw_pc_wrclk | en_dw_pc_wrclk_gating
hssi_8g_rx_pcs_clock_gate_dw_rm_rd | en_dw_rm_rdclk_gating
hssi_8g_rx_pcs_clock_gate_dw_rm_wr | en_dw_rm_wrclk_gating
hssi_8g_rx_pcs_clock_gate_dw_wa | en_dw_wa_clk_gating
hssi_8g_rx_pcs_clock_gate_pc_rdclk | en_pc_rdclk_gating
hssi_8g_rx_pcs_clock_gate_sw_pc_wrclk | en_sw_pc_wrclk_gating
hssi_8g_rx_pcs_clock_gate_sw_rm_rd | en_sw_rm_rdclk_gating
hssi_8g_rx_pcs_clock_gate_sw_rm_wr | en_sw_rm_wrclk_gating
hssi_8g_rx_pcs_clock_gate_sw_wa | en_sw_wa_clk_gating
hssi_8g_rx_pcs_clock_observation_in_pld_core | internal_sw_wa_clk
hssi_8g_rx_pcs_ctrl_plane_bonding_compensation | dis_compensation
hssi_8g_rx_pcs_ctrl_plane_bonding_consumption | individual
hssi_8g_rx_pcs_ctrl_plane_bonding_distribution | not_master_chnl_distr
hssi_8g_rx_pcs_eidle_entry_eios | dis_eidle_eios
hssi_8g_rx_pcs_eidle_entry_iei | dis_eidle_iei
hssi_8g_rx_pcs_eidle_entry_sd | dis_eidle_sd
hssi_8g_rx_pcs_eightb_tenb_decoder | en_8b10b_ibm
hssi_8g_rx_pcs_err_flags_sel | err_flags_wa
hssi_8g_rx_pcs_fixed_pat_det | dis_fixed_patdet
hssi_8g_rx_pcs_fixed_pat_num | 0
hssi_8g_rx_pcs_force_signal_detect | en_force_signal_detect
hssi_8g_rx_pcs_gen3_clk_en | disable_clk
hssi_8g_rx_pcs_gen3_rx_clk_sel | rcvd_clk
hssi_8g_rx_pcs_gen3_tx_clk_sel | tx_pma_clk
hssi_8g_rx_pcs_hip_mode | dis_hip
hssi_8g_rx_pcs_ibm_invalid_code | dis_ibm_invalid_code
hssi_8g_rx_pcs_invalid_code_flag_only | dis_invalid_code_only
hssi_8g_rx_pcs_pad_or_edb_error_replace | replace_edb
hssi_8g_rx_pcs_pcs_bypass | dis_pcs_bypass
hssi_8g_rx_pcs_phase_comp_rdptr | disable_rdptr
hssi_8g_rx_pcs_phase_compensation_fifo | low_latency
hssi_8g_rx_pcs_pipe_if_enable | dis_pipe_rx
hssi_8g_rx_pcs_pma_dw | ten_bit
hssi_8g_rx_pcs_polinv_8b10b_dec | dis_polinv_8b10b_dec
hssi_8g_rx_pcs_prot_mode | disabled_prot_mode
hssi_8g_rx_pcs_rate_match | dis_rm
hssi_8g_rx_pcs_rate_match_del_thres | dis_rm_del_thres
hssi_8g_rx_pcs_rate_match_empty_thres | dis_rm_empty_thres
hssi_8g_rx_pcs_rate_match_full_thres | dis_rm_full_thres
hssi_8g_rx_pcs_rate_match_ins_thres | dis_rm_ins_thres
hssi_8g_rx_pcs_rate_match_start_thres | dis_rm_start_thres
hssi_8g_rx_pcs_rx_clk_free_running | en_rx_clk_free_run
hssi_8g_rx_pcs_rx_clk2 | rcvd_clk_clk2
hssi_8g_rx_pcs_rx_pcs_urst | en_rx_pcs_urst
hssi_8g_rx_pcs_rx_rcvd_clk | rcvd_clk_rcvd_clk
hssi_8g_rx_pcs_rx_rd_clk | pld_rx_clk
hssi_8g_rx_pcs_rx_refclk | dis_refclk_sel
hssi_8g_rx_pcs_rx_wr_clk | rx_clk2_div_1_2_4
hssi_8g_rx_pcs_sup_mode | user_mode
hssi_8g_rx_pcs_symbol_swap | dis_symbol_swap
hssi_8g_rx_pcs_sync_sm_idle_eios | dis_syncsm_idle
hssi_8g_rx_pcs_test_bus_sel | tx_testbus
hssi_8g_rx_pcs_tx_rx_parallel_loopback | dis_plpbk
hssi_8g_rx_pcs_wa_boundary_lock_ctrl | sync_sm
hssi_8g_rx_pcs_wa_clk_slip_spacing | 16
hssi_8g_rx_pcs_wa_det_latency_sync_status_beh | dont_care_assert_sync
hssi_8g_rx_pcs_wa_disp_err_flag | en_disp_err_flag
hssi_8g_rx_pcs_wa_kchar | dis_kchar
hssi_8g_rx_pcs_wa_pd | wa_pd_10
hssi_8g_rx_pcs_wa_pd_data | 0
hssi_8g_rx_pcs_wa_pd_polarity | dont_care_both_pol
hssi_8g_rx_pcs_wa_pld_controlled | dis_pld_ctrl
hssi_8g_rx_pcs_wa_renumber_data | 3
hssi_8g_rx_pcs_wa_rgnumber_data | 3
hssi_8g_rx_pcs_wa_rknumber_data | 3
hssi_8g_rx_pcs_wa_rosnumber_data | 1
hssi_8g_rx_pcs_wa_rvnumber_data | 0
hssi_8g_rx_pcs_wa_sync_sm_ctrl | gige_sync_sm
hssi_8g_rx_pcs_wait_cnt | 0
hssi_8g_rx_pcs_silicon_rev | 20nm5es
hssi_8g_rx_pcs_reconfig_settings | {}
hssi_8g_tx_pcs_auto_speed_nego_gen2 | dis_asn_g2
hssi_8g_tx_pcs_bit_reversal | dis_bit_reversal
hssi_8g_tx_pcs_bonding_dft_en | dft_dis
hssi_8g_tx_pcs_bonding_dft_val | dft_0
hssi_8g_tx_pcs_bypass_pipeline_reg | dis_bypass_pipeline
hssi_8g_tx_pcs_byte_serializer | dis_bs
hssi_8g_tx_pcs_clock_gate_bs_enc | en_bs_enc_clk_gating
hssi_8g_tx_pcs_clock_gate_dw_fifowr | en_dw_fifowr_clk_gating
hssi_8g_tx_pcs_clock_gate_fiford | en_fiford_clk_gating
hssi_8g_tx_pcs_clock_gate_sw_fifowr | en_sw_fifowr_clk_gating
hssi_8g_tx_pcs_clock_observation_in_pld_core | internal_refclk_b
hssi_8g_tx_pcs_ctrl_plane_bonding_compensation | dis_compensation
hssi_8g_tx_pcs_ctrl_plane_bonding_consumption | individual
hssi_8g_tx_pcs_ctrl_plane_bonding_distribution | not_master_chnl_distr
hssi_8g_tx_pcs_data_selection_8b10b_encoder_input | normal_data_path
hssi_8g_tx_pcs_dynamic_clk_switch | dis_dyn_clk_switch
hssi_8g_tx_pcs_eightb_tenb_disp_ctrl | dis_disp_ctrl
hssi_8g_tx_pcs_eightb_tenb_encoder | en_8b10b_ibm
hssi_8g_tx_pcs_force_echar | dis_force_echar
hssi_8g_tx_pcs_force_kchar | dis_force_kchar
hssi_8g_tx_pcs_gen3_tx_clk_sel | dis_tx_clk
hssi_8g_tx_pcs_gen3_tx_pipe_clk_sel | dis_tx_pipe_clk
hssi_8g_tx_pcs_hip_mode | dis_hip
hssi_8g_tx_pcs_pcs_bypass | dis_pcs_bypass
hssi_8g_tx_pcs_phase_comp_rdptr | disable_rdptr
hssi_8g_tx_pcs_phase_compensation_fifo | low_latency
hssi_8g_tx_pcs_phfifo_write_clk_sel | pld_tx_clk
hssi_8g_tx_pcs_pma_dw | ten_bit
hssi_8g_tx_pcs_prot_mode | disabled_prot_mode
hssi_8g_tx_pcs_refclk_b_clk_sel | tx_pma_clock
hssi_8g_tx_pcs_revloop_back_rm | dis_rev_loopback_rx_rm
hssi_8g_tx_pcs_sup_mode | user_mode
hssi_8g_tx_pcs_symbol_swap | dis_symbol_swap
hssi_8g_tx_pcs_tx_bitslip | dis_tx_bitslip
hssi_8g_tx_pcs_tx_compliance_controlled_disparity | dis_txcompliance
hssi_8g_tx_pcs_tx_fast_pld_reg | dis_tx_fast_pld_reg
hssi_8g_tx_pcs_txclk_freerun | en_freerun_tx
hssi_8g_tx_pcs_txpcs_urst | en_txpcs_urst
hssi_8g_tx_pcs_silicon_rev | 20nm5es
hssi_8g_tx_pcs_reconfig_settings | {}
hssi_tx_pld_pcs_interface_hd_chnl_hip_en | disable
hssi_tx_pld_pcs_interface_hd_chnl_hrdrstctl_en | disable
hssi_tx_pld_pcs_interface_hd_chnl_prot_mode_tx | teng_baser_tx
hssi_tx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_tx | individual_tx
hssi_tx_pld_pcs_interface_hd_chnl_pma_dw_tx | pma_64b_tx
hssi_tx_pld_pcs_interface_hd_chnl_pld_fifo_mode_tx | fifo_tx
hssi_tx_pld_pcs_interface_hd_chnl_shared_fifo_width_tx | single_tx
hssi_tx_pld_pcs_interface_hd_chnl_low_latency_en_tx | disable
hssi_tx_pld_pcs_interface_hd_chnl_func_mode | enable
hssi_tx_pld_pcs_interface_hd_chnl_sup_mode | user_mode
hssi_tx_pld_pcs_interface_hd_chnl_channel_operation_mode | tx_rx_pair_enabled
hssi_tx_pld_pcs_interface_hd_chnl_lpbk_en | disable
hssi_tx_pld_pcs_interface_hd_chnl_frequency_rules_en | enable
hssi_tx_pld_pcs_interface_hd_chnl_speed_grade | e3
hssi_tx_pld_pcs_interface_hd_chnl_pma_tx_clk_hz | 168750000
hssi_tx_pld_pcs_interface_hd_chnl_pld_tx_clk_hz | 163636363
hssi_tx_pld_pcs_interface_hd_chnl_pld_uhsif_tx_clk_hz | 0
hssi_tx_pld_pcs_interface_hd_chnl_hclk_clk_hz | 0
hssi_tx_pld_pcs_interface_hd_chnl_pld_pcs_refclk_dig_nonatpg_mode_clk_hz | 0
hssi_tx_pld_pcs_interface_hd_chnl_pld_8g_refclk_dig_nonatpg_mode_clk_hz | 0
hssi_tx_pld_pcs_interface_hd_chnl_pcs_tx_ac_pwr_uw_per_mhz | 0
hssi_tx_pld_pcs_interface_hd_chnl_pcs_tx_pwr_scaling_clk | pma_tx_clk
hssi_tx_pld_pcs_interface_hd_fifo_sup_mode | user_mode
hssi_tx_pld_pcs_interface_hd_fifo_channel_operation_mode | tx_rx_pair_enabled
hssi_tx_pld_pcs_interface_hd_fifo_prot_mode_tx | teng_mode_tx
hssi_tx_pld_pcs_interface_hd_fifo_shared_fifo_width_tx | single_tx
hssi_tx_pld_pcs_interface_hd_10g_sup_mode | user_mode
hssi_tx_pld_pcs_interface_hd_10g_channel_operation_mode | tx_rx_pair_enabled
hssi_tx_pld_pcs_interface_hd_10g_lpbk_en | disable
hssi_tx_pld_pcs_interface_hd_10g_advanced_user_mode_tx | disable
hssi_tx_pld_pcs_interface_hd_10g_pma_dw_tx | pma_64b_tx
hssi_tx_pld_pcs_interface_hd_10g_fifo_mode_tx | fifo_tx
hssi_tx_pld_pcs_interface_hd_10g_prot_mode_tx | teng_baser_mode_tx
hssi_tx_pld_pcs_interface_hd_10g_ctrl_plane_bonding_tx | individual_tx
hssi_tx_pld_pcs_interface_hd_10g_low_latency_en_tx | disable
hssi_tx_pld_pcs_interface_hd_10g_shared_fifo_width_tx | single_tx
hssi_tx_pld_pcs_interface_hd_8g_sup_mode | user_mode
hssi_tx_pld_pcs_interface_hd_8g_channel_operation_mode | tx_rx_pair_enabled
hssi_tx_pld_pcs_interface_hd_8g_lpbk_en | disable
hssi_tx_pld_pcs_interface_hd_8g_prot_mode_tx | disabled_prot_mode_tx
hssi_tx_pld_pcs_interface_hd_8g_hip_mode | disable
hssi_tx_pld_pcs_interface_hd_8g_ctrl_plane_bonding_tx | ctrl_master_tx
hssi_tx_pld_pcs_interface_hd_8g_pma_dw_tx | pma_10b_tx
hssi_tx_pld_pcs_interface_hd_8g_fifo_mode_tx | fifo_tx
hssi_tx_pld_pcs_interface_hd_g3_sup_mode | user_mode
hssi_tx_pld_pcs_interface_hd_g3_prot_mode | disabled_prot_mode
hssi_tx_pld_pcs_interface_hd_krfec_sup_mode | user_mode
hssi_tx_pld_pcs_interface_hd_krfec_channel_operation_mode | tx_rx_pair_enabled
hssi_tx_pld_pcs_interface_hd_krfec_lpbk_en | disable
hssi_tx_pld_pcs_interface_hd_krfec_prot_mode_tx | disabled_prot_mode_tx
hssi_tx_pld_pcs_interface_hd_krfec_low_latency_en_tx | disable
hssi_tx_pld_pcs_interface_hd_pmaif_sup_mode | user_mode
hssi_tx_pld_pcs_interface_hd_pmaif_lpbk_en | disable
hssi_tx_pld_pcs_interface_hd_pmaif_channel_operation_mode | tx_rx_pair_enabled
hssi_tx_pld_pcs_interface_hd_pmaif_sim_mode | disable
hssi_tx_pld_pcs_interface_hd_pmaif_prot_mode_tx | teng_krfec_mode_tx
hssi_tx_pld_pcs_interface_hd_pmaif_ctrl_plane_bonding | individual
hssi_tx_pld_pcs_interface_hd_pmaif_pma_dw_tx | pma_64b_tx
hssi_tx_pld_pcs_interface_hd_pldif_prot_mode_tx | teng_pld_fifo_mode_tx
hssi_tx_pld_pcs_interface_hd_pldif_hrdrstctl_en | disable
hssi_tx_pld_pcs_interface_hd_pldif_sup_mode | user_mode
hssi_tx_pld_pcs_interface_pcs_tx_clk_source | teng
hssi_tx_pld_pcs_interface_pcs_tx_data_source | hip_disable
hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_en | delay1_clk_disable
hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_sel | pcs_tx_clk
hssi_tx_pld_pcs_interface_pcs_tx_delay1_ctrl | delay1_path0
hssi_tx_pld_pcs_interface_pcs_tx_delay1_data_sel | one_ff_delay
hssi_tx_pld_pcs_interface_pcs_tx_delay2_clk_en | delay2_clk_disable
hssi_tx_pld_pcs_interface_pcs_tx_delay2_ctrl | delay2_path0
hssi_tx_pld_pcs_interface_pcs_tx_output_sel | teng_output
hssi_tx_pld_pcs_interface_silicon_rev | 20nm5es
hssi_tx_pld_pcs_interface_pcs_tx_clk_out_sel | teng_clk_out
hssi_tx_pld_pcs_interface_reconfig_settings | {}
hssi_rx_pld_pcs_interface_hd_chnl_hip_en | disable
hssi_rx_pld_pcs_interface_hd_chnl_transparent_pcs_rx | disable
hssi_rx_pld_pcs_interface_hd_chnl_hrdrstctl_en | disable
hssi_rx_pld_pcs_interface_hd_chnl_prot_mode_rx | teng_baser_rx
hssi_rx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_rx | individual_rx
hssi_rx_pld_pcs_interface_hd_chnl_pma_dw_rx | pma_64b_rx
hssi_rx_pld_pcs_interface_hd_chnl_pld_fifo_mode_rx | fifo_rx
hssi_rx_pld_pcs_interface_hd_chnl_shared_fifo_width_rx | single_rx
hssi_rx_pld_pcs_interface_hd_chnl_low_latency_en_rx | disable
hssi_rx_pld_pcs_interface_hd_chnl_func_mode | enable
hssi_rx_pld_pcs_interface_hd_chnl_sup_mode | user_mode
hssi_rx_pld_pcs_interface_hd_chnl_channel_operation_mode | tx_rx_pair_enabled
hssi_rx_pld_pcs_interface_hd_chnl_lpbk_en | disable
hssi_rx_pld_pcs_interface_hd_10g_advanced_user_mode_rx | disable
hssi_rx_pld_pcs_interface_hd_chnl_frequency_rules_en | enable
hssi_rx_pld_pcs_interface_hd_chnl_speed_grade | e3
hssi_rx_pld_pcs_interface_hd_chnl_pma_rx_clk_hz | 168750000
hssi_rx_pld_pcs_interface_hd_chnl_pld_rx_clk_hz | 163636363
hssi_rx_pld_pcs_interface_hd_chnl_fref_clk_hz | 270000000
hssi_rx_pld_pcs_interface_hd_chnl_clklow_clk_hz | 270000000
hssi_rx_pld_pcs_interface_hd_chnl_hclk_clk_hz | 0
hssi_rx_pld_pcs_interface_hd_chnl_pld_pcs_refclk_dig_nonatpg_mode_clk_hz | 0
hssi_rx_pld_pcs_interface_hd_chnl_pld_8g_refclk_dig_nonatpg_mode_clk_hz | 0
hssi_rx_pld_pcs_interface_hd_chnl_pcs_rx_ac_pwr_uw_per_mhz | 0
hssi_rx_pld_pcs_interface_hd_chnl_operating_voltage | standard
hssi_rx_pld_pcs_interface_hd_chnl_pcs_ac_pwr_rules_en | disable
hssi_rx_pld_pcs_interface_hd_chnl_pcs_rx_pwr_scaling_clk | pma_rx_clk
hssi_rx_pld_pcs_interface_hd_chnl_pcs_pair_ac_pwr_uw_per_mhz | 0
hssi_rx_pld_pcs_interface_hd_fifo_sup_mode | user_mode
hssi_rx_pld_pcs_interface_hd_fifo_channel_operation_mode | tx_rx_pair_enabled
hssi_rx_pld_pcs_interface_hd_fifo_prot_mode_rx | teng_mode_rx
hssi_rx_pld_pcs_interface_hd_fifo_shared_fifo_width_rx | single_rx
hssi_rx_pld_pcs_interface_hd_10g_sup_mode | user_mode
hssi_rx_pld_pcs_interface_hd_10g_channel_operation_mode | tx_rx_pair_enabled
hssi_rx_pld_pcs_interface_hd_10g_lpbk_en | disable
hssi_rx_pld_pcs_interface_hd_10g_pma_dw_rx | pma_64b_rx
hssi_rx_pld_pcs_interface_hd_10g_fifo_mode_rx | fifo_rx
hssi_rx_pld_pcs_interface_hd_10g_prot_mode_rx | teng_baser_mode_rx
hssi_rx_pld_pcs_interface_hd_10g_ctrl_plane_bonding_rx | individual_rx
hssi_rx_pld_pcs_interface_hd_10g_low_latency_en_rx | disable
hssi_rx_pld_pcs_interface_hd_10g_shared_fifo_width_rx | single_rx
hssi_rx_pld_pcs_interface_hd_10g_test_bus_mode | rx
hssi_rx_pld_pcs_interface_hd_8g_sup_mode | user_mode
hssi_rx_pld_pcs_interface_hd_8g_channel_operation_mode | tx_rx_pair_enabled
hssi_rx_pld_pcs_interface_hd_8g_lpbk_en | disable
hssi_rx_pld_pcs_interface_hd_8g_prot_mode_rx | disabled_prot_mode_rx
hssi_rx_pld_pcs_interface_hd_8g_hip_mode | disable
hssi_rx_pld_pcs_interface_hd_8g_ctrl_plane_bonding_rx | individual_rx
hssi_rx_pld_pcs_interface_hd_8g_pma_dw_rx | pma_10b_rx
hssi_rx_pld_pcs_interface_hd_8g_fifo_mode_rx | fifo_rx
hssi_rx_pld_pcs_interface_hd_g3_sup_mode | user_mode
hssi_rx_pld_pcs_interface_hd_g3_prot_mode | disabled_prot_mode
hssi_rx_pld_pcs_interface_hd_krfec_sup_mode | user_mode
hssi_rx_pld_pcs_interface_hd_krfec_channel_operation_mode | tx_rx_pair_enabled
hssi_rx_pld_pcs_interface_hd_krfec_lpbk_en | disable
hssi_rx_pld_pcs_interface_hd_krfec_prot_mode_rx | disabled_prot_mode_rx
hssi_rx_pld_pcs_interface_hd_krfec_low_latency_en_rx | disable
hssi_rx_pld_pcs_interface_hd_krfec_test_bus_mode | tx
hssi_rx_pld_pcs_interface_hd_pmaif_sup_mode | user_mode
hssi_rx_pld_pcs_interface_hd_pmaif_lpbk_en | disable
hssi_rx_pld_pcs_interface_hd_pmaif_channel_operation_mode | tx_rx_pair_enabled
hssi_rx_pld_pcs_interface_hd_pmaif_sim_mode | disable
hssi_rx_pld_pcs_interface_hd_pmaif_prot_mode_rx | teng_krfec_mode_rx
hssi_rx_pld_pcs_interface_hd_pmaif_pma_dw_rx | pma_64b_rx
hssi_rx_pld_pcs_interface_hd_pldif_prot_mode_rx | teng_pld_fifo_mode_rx
hssi_rx_pld_pcs_interface_hd_pldif_hrdrstctl_en | disable
hssi_rx_pld_pcs_interface_hd_pldif_sup_mode | user_mode
hssi_rx_pld_pcs_interface_pcs_rx_block_sel | teng
hssi_rx_pld_pcs_interface_pcs_rx_clk_sel | pld_rx_clk
hssi_rx_pld_pcs_interface_pcs_rx_hip_clk_en | hip_rx_disable
hssi_rx_pld_pcs_interface_pcs_rx_output_sel | teng_output
hssi_rx_pld_pcs_interface_silicon_rev | 20nm5es
hssi_rx_pld_pcs_interface_pcs_rx_clk_out_sel | teng_clk_out
hssi_rx_pld_pcs_interface_reconfig_settings | {}
hssi_common_pld_pcs_interface_dft_clk_out_en | dft_clk_out_disable
hssi_common_pld_pcs_interface_dft_clk_out_sel | teng_rx_dft_clk
hssi_common_pld_pcs_interface_hrdrstctrl_en | hrst_dis
hssi_common_pld_pcs_interface_pcs_testbus_block_sel | pma_if
hssi_common_pld_pcs_interface_silicon_rev | 20nm5es
hssi_common_pld_pcs_interface_reconfig_settings | {}
hssi_rx_pcs_pma_interface_block_sel | ten_g_pcs
hssi_rx_pcs_pma_interface_channel_operation_mode | tx_rx_pair_enabled
hssi_rx_pcs_pma_interface_clkslip_sel | pld
hssi_rx_pcs_pma_interface_lpbk_en | disable
hssi_rx_pcs_pma_interface_master_clk_sel | master_rx_pma_clk
hssi_rx_pcs_pma_interface_pldif_datawidth_mode | pldif_data_10bit
hssi_rx_pcs_pma_interface_pma_dw_rx | pma_64b_rx
hssi_rx_pcs_pma_interface_pma_if_dft_en | dft_dis
hssi_rx_pcs_pma_interface_pma_if_dft_val | dft_0
hssi_rx_pcs_pma_interface_prbs_clken | prbs_clk_dis
hssi_rx_pcs_pma_interface_prbs_ver | prbs_off
hssi_rx_pcs_pma_interface_prbs9_dwidth | prbs9_64b
hssi_rx_pcs_pma_interface_prot_mode_rx | teng_krfec_mode_rx
hssi_rx_pcs_pma_interface_rx_dyn_polarity_inversion | rx_dyn_polinv_dis
hssi_rx_pcs_pma_interface_rx_lpbk_en | lpbk_dis
hssi_rx_pcs_pma_interface_rx_prbs_force_signal_ok | force_sig_ok
hssi_rx_pcs_pma_interface_rx_prbs_mask | prbsmask128
hssi_rx_pcs_pma_interface_rx_prbs_mode | teng_mode
hssi_rx_pcs_pma_interface_rx_signalok_signaldet_sel | sel_sig_det
hssi_rx_pcs_pma_interface_rx_static_polarity_inversion | rx_stat_polinv_dis
hssi_rx_pcs_pma_interface_rx_uhsif_lpbk_en | uhsif_lpbk_dis
hssi_rx_pcs_pma_interface_sup_mode | user_mode
hssi_rx_pcs_pma_interface_silicon_rev | 20nm5es
hssi_rx_pcs_pma_interface_reconfig_settings | {}
hssi_tx_pcs_pma_interface_bypass_pma_txelecidle | true
hssi_tx_pcs_pma_interface_channel_operation_mode | tx_rx_pair_enabled
hssi_tx_pcs_pma_interface_lpbk_en | disable
hssi_tx_pcs_pma_interface_master_clk_sel | master_tx_pma_clk
hssi_tx_pcs_pma_interface_pcie_sub_prot_mode_tx | other_prot_mode
hssi_tx_pcs_pma_interface_pldif_datawidth_mode | pldif_data_10bit
hssi_tx_pcs_pma_interface_pma_dw_tx | pma_64b_tx
hssi_tx_pcs_pma_interface_pma_if_dft_en | dft_dis
hssi_tx_pcs_pma_interface_pmagate_en | pmagate_dis
hssi_tx_pcs_pma_interface_prbs_clken | prbs_clk_dis
hssi_tx_pcs_pma_interface_prbs_gen_pat | prbs_gen_dis
hssi_tx_pcs_pma_interface_prbs9_dwidth | prbs9_64b
hssi_tx_pcs_pma_interface_prot_mode_tx | teng_krfec_mode_tx
hssi_tx_pcs_pma_interface_sq_wave_num | sq_wave_default
hssi_tx_pcs_pma_interface_sqwgen_clken | sqwgen_clk_dis
hssi_tx_pcs_pma_interface_sup_mode | user_mode
hssi_tx_pcs_pma_interface_tx_dyn_polarity_inversion | tx_dyn_polinv_dis
hssi_tx_pcs_pma_interface_tx_pma_data_sel | ten_g_pcs
hssi_tx_pcs_pma_interface_tx_static_polarity_inversion | tx_stat_polinv_dis
hssi_tx_pcs_pma_interface_uhsif_cnt_step_filt_before_lock | uhsif_filt_stepsz_b4lock_2
hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_after_lock_value | 0
hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_before_lock | uhsif_filt_cntthr_b4lock_8
hssi_tx_pcs_pma_interface_uhsif_dcn_test_update_period | uhsif_dcn_test_period_4
hssi_tx_pcs_pma_interface_uhsif_dcn_testmode_enable | uhsif_dcn_test_mode_disable
hssi_tx_pcs_pma_interface_uhsif_dead_zone_count_thresh | uhsif_dzt_cnt_thr_2
hssi_tx_pcs_pma_interface_uhsif_dead_zone_detection_enable | uhsif_dzt_disable
hssi_tx_pcs_pma_interface_uhsif_dead_zone_obser_window | uhsif_dzt_obr_win_16
hssi_tx_pcs_pma_interface_uhsif_dead_zone_skip_size | uhsif_dzt_skipsz_4
hssi_tx_pcs_pma_interface_uhsif_delay_cell_index_sel | uhsif_index_cram
hssi_tx_pcs_pma_interface_uhsif_delay_cell_margin | uhsif_dcn_margin_2
hssi_tx_pcs_pma_interface_uhsif_delay_cell_static_index_value | 0
hssi_tx_pcs_pma_interface_uhsif_dft_dead_zone_control | uhsif_dft_dz_det_val_0
hssi_tx_pcs_pma_interface_uhsif_dft_up_filt_control | uhsif_dft_up_val_0
hssi_tx_pcs_pma_interface_uhsif_enable | uhsif_disable
hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_after_lock | uhsif_lkd_segsz_aflock_512
hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_before_lock | uhsif_lkd_segsz_b4lock_16
hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_after_lock_value | 0
hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_before_lock_value | 0
hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_after_lock_value | 0
hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_before_lock_value | 0
hssi_tx_pcs_pma_interface_silicon_rev | 20nm5es
hssi_tx_pcs_pma_interface_reconfig_settings | {}
hssi_common_pcs_pma_interface_asn_clk_enable | false
hssi_common_pcs_pma_interface_asn_enable | dis_asn
hssi_common_pcs_pma_interface_block_sel | eight_g_pcs
hssi_common_pcs_pma_interface_bypass_early_eios | true
hssi_common_pcs_pma_interface_bypass_pcie_switch | true
hssi_common_pcs_pma_interface_bypass_pma_ltr | true
hssi_common_pcs_pma_interface_bypass_pma_sw_done | true
hssi_common_pcs_pma_interface_bypass_ppm_lock | false
hssi_common_pcs_pma_interface_bypass_send_syncp_fbkp | true
hssi_common_pcs_pma_interface_bypass_txdetectrx | true
hssi_common_pcs_pma_interface_cdr_control | dis_cdr_ctrl
hssi_common_pcs_pma_interface_cid_enable | dis_cid_mode
hssi_common_pcs_pma_interface_cp_cons_sel | cp_cons_master
hssi_common_pcs_pma_interface_cp_dwn_mstr | true
hssi_common_pcs_pma_interface_cp_up_mstr | true
hssi_common_pcs_pma_interface_ctrl_plane_bonding | individual
hssi_common_pcs_pma_interface_data_mask_count | 0
hssi_common_pcs_pma_interface_data_mask_count_multi | 0
hssi_common_pcs_pma_interface_dft_observation_clock_selection | dft_clk_obsrv_tx0
hssi_common_pcs_pma_interface_early_eios_counter | 0
hssi_common_pcs_pma_interface_force_freqdet | force_freqdet_dis
hssi_common_pcs_pma_interface_free_run_clk_enable | false
hssi_common_pcs_pma_interface_ignore_sigdet_g23 | false
hssi_common_pcs_pma_interface_pc_en_counter | 0
hssi_common_pcs_pma_interface_pc_rst_counter | 0
hssi_common_pcs_pma_interface_pcie_hip_mode | hip_disable
hssi_common_pcs_pma_interface_ph_fifo_reg_mode | phfifo_reg_mode_dis
hssi_common_pcs_pma_interface_phfifo_flush_wait | 0
hssi_common_pcs_pma_interface_pipe_if_g3pcs | pipe_if_8gpcs
hssi_common_pcs_pma_interface_pma_done_counter | 0
hssi_common_pcs_pma_interface_pma_if_dft_en | dft_dis
hssi_common_pcs_pma_interface_pma_if_dft_val | dft_0
hssi_common_pcs_pma_interface_ppm_cnt_rst | ppm_cnt_rst_dis
hssi_common_pcs_pma_interface_ppm_deassert_early | deassert_early_dis
hssi_common_pcs_pma_interface_ppm_gen1_2_cnt | cnt_32k
hssi_common_pcs_pma_interface_ppm_post_eidle_delay | cnt_200_cycles
hssi_common_pcs_pma_interface_ppmsel | ppmsel_1000
hssi_common_pcs_pma_interface_prot_mode | other_protocols
hssi_common_pcs_pma_interface_rxvalid_mask | rxvalid_mask_dis
hssi_common_pcs_pma_interface_sigdet_wait_counter | 0
hssi_common_pcs_pma_interface_sigdet_wait_counter_multi | 0
hssi_common_pcs_pma_interface_sim_mode | disable
hssi_common_pcs_pma_interface_spd_chg_rst_wait_cnt_en | false
hssi_common_pcs_pma_interface_sup_mode | user_mode
hssi_common_pcs_pma_interface_testout_sel | asn_test
hssi_common_pcs_pma_interface_wait_clk_on_off_timer | 0
hssi_common_pcs_pma_interface_wait_pipe_synchronizing | 0
hssi_common_pcs_pma_interface_wait_send_syncp_fbkp | 0
hssi_common_pcs_pma_interface_silicon_rev | 20nm5es
hssi_common_pcs_pma_interface_ppm_det_buckets | ppm_100_bucket
hssi_common_pcs_pma_interface_reconfig_settings | {}
hssi_fifo_rx_pcs_double_read_mode | double_read_dis
hssi_fifo_rx_pcs_prot_mode | teng_mode
hssi_fifo_rx_pcs_silicon_rev | 20nm5es
hssi_fifo_tx_pcs_double_write_mode | double_write_dis
hssi_fifo_tx_pcs_prot_mode | teng_mode
hssi_fifo_tx_pcs_silicon_rev | 20nm5es
hssi_pipe_gen3_bypass_rx_detection_enable | false
hssi_pipe_gen3_bypass_rx_preset | 0
hssi_pipe_gen3_bypass_rx_preset_enable | false
hssi_pipe_gen3_bypass_tx_coefficent | 0
hssi_pipe_gen3_bypass_tx_coefficent_enable | false
hssi_pipe_gen3_elecidle_delay_g3 | 0
hssi_pipe_gen3_ind_error_reporting | dis_ind_error_reporting
hssi_pipe_gen3_mode | disable_pcs
hssi_pipe_gen3_phy_status_delay_g12 | 0
hssi_pipe_gen3_phy_status_delay_g3 | 0
hssi_pipe_gen3_phystatus_rst_toggle_g12 | dis_phystatus_rst_toggle
hssi_pipe_gen3_phystatus_rst_toggle_g3 | dis_phystatus_rst_toggle_g3
hssi_pipe_gen3_rate_match_pad_insertion | dis_rm_fifo_pad_ins
hssi_pipe_gen3_sup_mode | user_mode
hssi_pipe_gen3_test_out_sel | disable_test_out
hssi_pipe_gen3_silicon_rev | 20nm5es
hssi_pipe_gen1_2_elec_idle_delay_val | 0
hssi_pipe_gen1_2_error_replace_pad | replace_edb
hssi_pipe_gen1_2_hip_mode | dis_hip
hssi_pipe_gen1_2_ind_error_reporting | dis_ind_error_reporting
hssi_pipe_gen1_2_phystatus_delay_val | 0
hssi_pipe_gen1_2_phystatus_rst_toggle | dis_phystatus_rst_toggle
hssi_pipe_gen1_2_pipe_byte_de_serializer_en | dont_care_bds
hssi_pipe_gen1_2_prot_mode | disabled_prot_mode
hssi_pipe_gen1_2_rpre_emph_a_val | 0
hssi_pipe_gen1_2_rpre_emph_b_val | 0
hssi_pipe_gen1_2_rpre_emph_c_val | 0
hssi_pipe_gen1_2_rpre_emph_d_val | 0
hssi_pipe_gen1_2_rpre_emph_e_val | 0
hssi_pipe_gen1_2_rvod_sel_a_val | 0
hssi_pipe_gen1_2_rvod_sel_b_val | 0
hssi_pipe_gen1_2_rvod_sel_c_val | 0
hssi_pipe_gen1_2_rvod_sel_d_val | 0
hssi_pipe_gen1_2_rvod_sel_e_val | 0
hssi_pipe_gen1_2_rx_pipe_enable | dis_pipe_rx
hssi_pipe_gen1_2_rxdetect_bypass | dis_rxdetect_bypass
hssi_pipe_gen1_2_sup_mode | user_mode
hssi_pipe_gen1_2_tx_pipe_enable | dis_pipe_tx
hssi_pipe_gen1_2_txswing | dis_txswing
hssi_pipe_gen1_2_silicon_rev | 20nm5es
hssi_pipe_gen1_2_reconfig_settings | {}
pma_adapt_silicon_rev | 20nm5es
pma_adapt_adp_1s_ctle_bypass | radp_1s_ctle_bypass_1
pma_adapt_adp_4s_ctle_bypass | radp_4s_ctle_bypass_1
pma_adapt_adp_ctle_acgain_4s | radp_ctle_acgain_4s_1
pma_adapt_adp_ctle_en | radp_ctle_disable
pma_adapt_adp_ctle_hold_en | radp_ctle_not_held
pma_adapt_adp_ctle_scale | radp_ctle_scale_0
pma_adapt_adp_dfe_bw | radp_dfe_bw_3
pma_adapt_adp_dfe_cycle | radp_dfe_cycle_6
pma_adapt_adp_dfe_fltap_bypass | radp_dfe_fltap_bypass_1
pma_adapt_adp_dfe_fltap_en | radp_dfe_fltap_disable
pma_adapt_adp_dfe_fltap_hold_en | radp_dfe_fltap_not_held
pma_adapt_adp_dfe_fltap_load | radp_dfe_fltap_load_0
pma_adapt_adp_dfe_fltap_position | radp_dfe_fltap_position_0
pma_adapt_adp_dfe_fxtap8 | radp_dfe_fxtap8_0
pma_adapt_adp_dfe_fxtap8_sgn | radp_dfe_fxtap8_sgn_0
pma_adapt_adp_dfe_fxtap9 | radp_dfe_fxtap9_0
pma_adapt_adp_dfe_fxtap9_sgn | radp_dfe_fxtap9_sgn_0
pma_adapt_adp_dfe_fxtap10 | radp_dfe_fxtap10_0
pma_adapt_adp_dfe_fxtap10_sgn | radp_dfe_fxtap10_sgn_0
pma_adapt_adp_dfe_fxtap11 | radp_dfe_fxtap11_0
pma_adapt_adp_dfe_fxtap11_sgn | radp_dfe_fxtap11_sgn_0
pma_adapt_adp_dfe_fxtap_bypass | radp_dfe_fxtap_bypass_1
pma_adapt_adp_dfe_fxtap_en | radp_dfe_fxtap_disable
pma_adapt_adp_dfe_fxtap_hold_en | radp_dfe_fxtap_not_held
pma_adapt_adp_dfe_fxtap_load | radp_dfe_fxtap_load_0
pma_adapt_adp_dfe_fxtap1 | radp_dfe_fxtap1_0
pma_adapt_adp_dfe_fxtap2 | radp_dfe_fxtap2_0
pma_adapt_adp_dfe_fxtap2_sgn | radp_dfe_fxtap2_sgn_0
pma_adapt_adp_dfe_fxtap3 | radp_dfe_fxtap3_0
pma_adapt_adp_dfe_fxtap3_sgn | radp_dfe_fxtap3_sgn_0
pma_adapt_adp_dfe_fxtap4 | radp_dfe_fxtap4_0
pma_adapt_adp_dfe_fxtap4_sgn | radp_dfe_fxtap4_sgn_0
pma_adapt_adp_dfe_fxtap5 | radp_dfe_fxtap5_0
pma_adapt_adp_dfe_fxtap5_sgn | radp_dfe_fxtap5_sgn_0
pma_adapt_adp_dfe_fxtap6 | radp_dfe_fxtap6_0
pma_adapt_adp_dfe_fxtap6_sgn | radp_dfe_fxtap6_sgn_0
pma_adapt_adp_dfe_fxtap7 | radp_dfe_fxtap7_0
pma_adapt_adp_dfe_fxtap7_sgn | radp_dfe_fxtap7_sgn_0
pma_adapt_adp_dfe_mode | radp_dfe_mode_4
pma_adapt_adp_dfe_vref_polarity | radp_dfe_vref_polarity_0
pma_adapt_adp_force_freqlock | radp_force_freqlock_off
pma_adapt_adp_lfeq_fb_sel | radp_lfeq_fb_sel_0
pma_adapt_adp_status_sel | radp_status_sel_0
pma_adapt_adp_vga_bypass | radp_vga_bypass_1
pma_adapt_adp_vga_en | radp_vga_disable
pma_adapt_adp_vga_polarity | radp_vga_polarity_0
pma_adapt_adp_vga_sel | radp_vga_sel_2
pma_adapt_adp_vga_sweep_direction | radp_vga_sweep_direction_1
pma_adapt_adp_vga_threshold | radp_vga_threshold_4
pma_adapt_adp_vref_bw | radp_vref_bw_1
pma_adapt_adp_vref_bypass | radp_vref_bypass_1
pma_adapt_adp_vref_cycle | radp_vref_cycle_6
pma_adapt_adp_vref_en | radp_vref_disable
pma_adapt_adp_vref_hold_en | radp_vref_not_held
pma_adapt_adp_vref_polarity | radp_vref_polarity_0
pma_adapt_adp_vref_sel | radp_vref_sel_21
pma_adapt_adp_vref_vga_level | radp_vref_vga_level_13
pma_adapt_datarate | 10800000000 bps
pma_adapt_odi_en | rodi_en_0
pma_adapt_odi_rstn | rodi_rstn_0
pma_adapt_odi_spec_sel | rodi_spec_sel_0
pma_adapt_odi_vref_sel | rodi_vref_sel_0
pma_adapt_optimal | true
pma_adapt_initial_settings | true
pma_adapt_prot_mode | basic_rx
pma_adapt_sup_mode | user_mode
pma_adapt_adapt_dfe_control_sel | r_adapt_dfe_control_sel_0
pma_adapt_adp_ctle_adapt_bw | radp_ctle_adapt_bw_3
pma_adapt_adp_dfe_spec_sign | radp_dfe_spec_sign_0
pma_adapt_adp_ctle_force_spec_sign | radp_ctle_force_spec_sign_0
pma_adapt_odi_mode | rodi_mode_0
pma_adapt_adp_ctle_threshold | radp_ctle_threshold_0
pma_adapt_adp_ctle_window | radp_ctle_window_0
pma_adapt_adp_ctle_threshold_en | radp_ctle_threshold_en_0
pma_adapt_adp_ctle_spec_sign | radp_ctle_spec_sign_0
pma_adapt_adp_odi_control_sel | radp_odi_control_sel_0
pma_adapt_adp_spec_avg_window | radp_spec_avg_window_4
pma_adapt_adp_ctle_adapt_cycle_window | radp_ctle_adapt_cycle_window_7
pma_adapt_odi_dfe_spec_en | rodi_dfe_spec_en_0
pma_adapt_adp_dfe_clkout_div_sel | radp_dfe_clkout_div_sel_0
pma_adapt_adp_ctle_load_value | radp_ctle_load_value_0
pma_adapt_rrx_pcie_eqz | rrx_pcie_eqz_0
pma_adapt_adp_bist_mode | radp_bist_mode_0
pma_adapt_adapt_dfe_sel | r_adapt_dfe_sel_0
pma_adapt_adp_spec_trans_filter | radp_spec_trans_filter_2
pma_adapt_adp_frame_en | radp_frame_en_0
pma_adapt_odi_count_threshold | rodi_count_threshold_0
pma_adapt_adp_bist_spec_en | radp_bist_spec_en_0
pma_adapt_adapt_mode | manual
pma_adapt_adp_ctle_adapt_oneshot | radp_ctle_adapt_oneshot_1
pma_adapt_adp_bist_auxpath_en | radp_bist_auxpath_disable
pma_adapt_adp_frame_out_sel | radp_frame_out_sel_0
pma_adapt_adapt_vga_sel | r_adapt_vga_sel_0
pma_adapt_adp_vref_load | radp_vref_load_0
pma_adapt_adp_ctle_scale_en | radp_ctle_scale_en_0
pma_adapt_adp_onetime_dfe | radp_onetime_dfe_0
pma_adapt_adp_dfe_force_spec_sign | radp_dfe_force_spec_sign_0
pma_adapt_adp_frame_odi_sel | radp_frame_odi_sel_0
pma_adapt_adp_bist_datapath_en | radp_bist_datapath_disable
pma_adapt_adp_control_mux_bypass | radp_control_mux_bypass_0
pma_adapt_adp_ctle_vref_polarity | radp_ctle_vref_polarity_0
pma_adapt_adp_bist_count_rstn | radp_bist_count_rstn_0
pma_adapt_adp_ctle_eqz_1s_sel | radp_ctle_eqz_1s_sel_3
pma_adapt_adp_vref_dfe_spec_en | radp_vref_dfe_spec_en_0
pma_adapt_adp_adapt_rstn | radp_adapt_rstn_1
pma_adapt_adp_adapt_start | radp_adapt_start_0
pma_adapt_odi_start | rodi_start_0
pma_adapt_adp_ctle_sweep_direction | radp_ctle_sweep_direction_1
pma_adapt_adp_vga_load | radp_vga_load_0
pma_adapt_adp_frame_capture | radp_frame_capture_0
pma_adapt_adp_adapt_control_sel | radp_adapt_control_sel_0
pma_adapt_adp_bist_odi_dfe_sel | radp_bist_odi_dfe_sel_0
pma_adapt_adapt_vref_sel | r_adapt_vref_sel_0
pma_adapt_adp_mode | radp_mode_8
pma_adapt_adp_ctle_load | radp_ctle_load_0
pma_cdr_refclk_cdr_clkin_scratch0_src | cdr_clkin_scratch0_src_refclk_iqclk
pma_cdr_refclk_cdr_clkin_scratch1_src | cdr_clkin_scratch1_src_refclk_iqclk
pma_cdr_refclk_cdr_clkin_scratch2_src | cdr_clkin_scratch2_src_refclk_iqclk
pma_cdr_refclk_cdr_clkin_scratch3_src | cdr_clkin_scratch3_src_refclk_iqclk
pma_cdr_refclk_cdr_clkin_scratch4_src | cdr_clkin_scratch4_src_refclk_iqclk
pma_cdr_refclk_powerdown_mode | powerup
pma_cdr_refclk_receiver_detect_src | iqclk_src
pma_cdr_refclk_xmux_refclk_src | refclk_iqclk
pma_cdr_refclk_xpm_iqref_mux_iqclk_sel | power_down
pma_cdr_refclk_xpm_iqref_mux_scratch0_src | scratch0_power_down
pma_cdr_refclk_xpm_iqref_mux_scratch1_src | scratch1_power_down
pma_cdr_refclk_xpm_iqref_mux_scratch2_src | scratch2_power_down
pma_cdr_refclk_xpm_iqref_mux_scratch3_src | scratch3_power_down
pma_cdr_refclk_xpm_iqref_mux_scratch4_src | scratch4_power_down
pma_cdr_refclk_refclk_select | ref_iqclk0
pma_cdr_refclk_silicon_rev | 20nm5es
pma_cdr_refclk_inclk0_logical_to_physical_mapping | ref_iqclk0
pma_cdr_refclk_inclk1_logical_to_physical_mapping | ref_iqclk0
pma_cdr_refclk_inclk2_logical_to_physical_mapping | ref_iqclk0
pma_cdr_refclk_inclk3_logical_to_physical_mapping | ref_iqclk0
pma_cdr_refclk_inclk4_logical_to_physical_mapping | ref_iqclk0
pma_cgb_silicon_rev | 20nm5es
pma_cgb_observe_cgb_clocks | observe_nothing
pma_cgb_bitslip_enable | disable_bitslip
pma_cgb_bonding_mode | x1_non_bonded
pma_cgb_bonding_reset_enable | disallow_bonding_reset
pma_cgb_cgb_power_down | normal_cgb
pma_cgb_datarate | 10800000000 bps
pma_cgb_pcie_gen3_bitwidth | pciegen3_wide
pma_cgb_prot_mode | basic_tx
pma_cgb_scratch0_x1_clock_src | unused
pma_cgb_scratch1_x1_clock_src | unused
pma_cgb_scratch2_x1_clock_src | unused
pma_cgb_scratch3_x1_clock_src | unused
pma_cgb_select_done_master_or_slave | choose_master_pcie_sw_done
pma_cgb_ser_mode | sixty_four_bit
pma_cgb_ser_powerdown | normal_poweron_ser
pma_cgb_sup_mode | user_mode
pma_cgb_vccdreg_output | vccdreg_nominal
pma_cgb_x1_clock_source_sel | cdr_txpll_t
pma_cgb_x1_div_m_sel | divbypass
pma_cgb_xn_clock_source_sel | sel_xn_up
pma_cgb_input_select_x1 | fpll_bot
pma_cgb_input_select_gen3 | unused
pma_cgb_input_select_xn | unused
pma_cgb_tx_ucontrol_reset | disable
pma_cgb_tx_ucontrol_en | disable
pma_cgb_initial_settings | true
pma_cgb_tx_ucontrol_pcie | gen1
pma_cgb_dprio_cgb_vreg_boost | no_voltage_boost
pma_rx_dfe_silicon_rev | 20nm5es
pma_rx_dfe_atb_select | atb_disable
pma_rx_dfe_datarate | 10800000000 bps
pma_rx_dfe_dft_en | dft_disable
pma_rx_dfe_oc_sa_c270 | 0
pma_rx_dfe_oc_sa_c90 | 0
pma_rx_dfe_oc_sa_d0c0 | 0
pma_rx_dfe_oc_sa_d0c180 | 0
pma_rx_dfe_oc_sa_d1c0 | 0
pma_rx_dfe_oc_sa_d1c180 | 0
pma_rx_dfe_optimal | true
pma_rx_dfe_pdb | dfe_enable
pma_rx_dfe_pdb_fixedtap | fixtap_dfe_powerdown
pma_rx_dfe_pdb_floattap | floattap_dfe_powerdown
pma_rx_dfe_pdb_fxtap4t7 | fxtap4t7_powerdown
pma_rx_dfe_power_mode | mid_power
pma_rx_dfe_sel_fltapstep_dec | fltap_step_no_dec
pma_rx_dfe_sel_fltapstep_inc | fltap_step_no_inc
pma_rx_dfe_sel_fxtapstep_dec | fxtap_step_no_dec
pma_rx_dfe_sel_fxtapstep_inc | fxtap_step_no_inc
pma_rx_dfe_sel_oc_en | off_canc_disable
pma_rx_dfe_sel_probe_tstmx | probe_tstmx_none
pma_rx_dfe_sup_mode | user_mode
pma_rx_dfe_uc_rx_dfe_cal | uc_rx_dfe_cal_off
pma_rx_dfe_uc_rx_dfe_cal_status | uc_rx_dfe_cal_notdone
pma_rx_dfe_oc_sa_adp1 | 0
pma_rx_dfe_oc_sa_adp2 | 0
pma_rx_dfe_initial_settings | true
pma_rx_dfe_prot_mode | basic_rx
pma_rx_odi_silicon_rev | 20nm5es
pma_rx_odi_datarate | 10800000000 bps
pma_rx_odi_enable_odi | power_down_eye
pma_rx_odi_monitor_bw_sel | bw_1
pma_rx_odi_optimal | true
pma_rx_odi_phase_steps_64_vs_128 | phase_steps_64
pma_rx_odi_phase_steps_sel | step40
pma_rx_odi_power_mode | mid_power
pma_rx_odi_sup_mode | user_mode
pma_rx_odi_v_vert_threshold_scaling | scale_3
pma_rx_odi_vert_threshold | vert_0
pma_rx_odi_oc_sa_c0 | 0
pma_rx_odi_initial_settings | true
pma_rx_odi_v_vert_sel | plus
pma_rx_odi_sel_oc_en | off_canc_disable
pma_rx_odi_clk_dcd_bypass | no_bypass
pma_rx_odi_invert_dfe_vref | no_inversion
pma_rx_odi_step_ctrl_sel | dprio_mode
pma_rx_odi_prot_mode | basic_rx
pma_rx_odi_oc_sa_c180 | 0
pma_rx_buf_silicon_rev | 20nm5es
pma_rx_buf_bypass_eqz_stages_234 | bypass_off
pma_rx_buf_cdrclk_to_cgb | cdrclk_2cgb_dis
pma_rx_buf_datarate | 10800000000 bps
pma_rx_buf_diag_lp_en | dlp_off
pma_rx_buf_eq_bw_sel | eq_bw_3
pma_rx_buf_input_vcm_sel | high_vcm
pma_rx_buf_link_rx | sr
pma_rx_buf_offset_cal_pd | eqz1_en
pma_rx_buf_offset_cancellation_ctrl | volt_0mv
pma_rx_buf_offset_pd | oc_en
pma_rx_buf_optimal | true
pma_rx_buf_pdb_rx | normal_rx_on
pma_rx_buf_power_mode_rx | mid_power
pma_rx_buf_prot_mode | basic_rx
pma_rx_buf_qpi_enable | non_qpi_mode
pma_rx_buf_rx_atb_select | atb_disable
pma_rx_buf_rx_refclk_divider | bypass_divider
pma_rx_buf_rx_sel_bias_source | bias_vcmdrv
pma_rx_buf_sup_mode | user_mode
pma_rx_buf_term_sel | r_r1
pma_rx_buf_vccela_supply_voltage | vccela_1p1v
pma_rx_buf_vcm_current_add | vcm_current_default
pma_rx_buf_vcm_sel | vcm_setting_03
pma_rx_buf_eq_dc_gain_trim | stg2_gain7
pma_rx_buf_offset_cancellation_coarse | coarse_setting_00
pma_rx_buf_bodybias_select | bodybias_sel1
pma_rx_buf_bodybias_enable | bodybias_en
pma_rx_buf_offset_cancellation_fine | fine_setting_00
pma_rx_buf_act_isource_disable | isrc_en
pma_rx_buf_one_stage_enable | s1_mode
pma_rx_buf_loopback_modes | lpbk_disable
pma_rx_buf_lfeq_zero_control | lfeq_setting_2
pma_rx_buf_initial_settings | true
pma_rx_buf_lfeq_enable | non_lfeq_mode
pma_rx_buf_term_tri_enable | disable_tri
pma_rx_buf_vga_bandwidth_select | vga_bw_1
pma_rx_buf_refclk_en | disable
pma_rx_buf_cgm_bias_disable | cgmbias_en
pma_rx_buf_pm_tx_rx_pcie_gen | non_pcie
pma_rx_buf_pm_tx_rx_pcie_gen_bitwidth | pcie_gen3_32b
pma_rx_buf_pm_tx_rx_cvp_mode | cvp_off
pma_rx_buf_pm_tx_rx_testmux_select | setting0
pma_rx_buf_xrx_path_jtag_hys | hys_increase_disable
pma_rx_buf_xrx_path_jtag_lp | lp_off
pma_rx_buf_xrx_path_uc_rx_rstb | rx_reset_on
pma_rx_buf_xrx_path_uc_pcie_sw | uc_pcie_gen1
pma_rx_buf_xrx_path_uc_cal_enable | rx_cal_off
pma_rx_buf_xrx_path_uc_cru_rstb | cdr_lf_reset_off
pma_rx_buf_xrx_path_sup_mode | user_mode
pma_rx_buf_power_rail_er | 1030
pma_rx_buf_power_rail_eht | 0
pma_rx_buf_xrx_path_gt_enabled | disable
pma_rx_buf_xrx_path_analog_mode | user_custom
pma_rx_buf_xrx_path_prot_mode | basic_rx
pma_rx_buf_pm_speed_grade | e2
pma_rx_buf_power_mode | mid_power
pma_rx_buf_iostandard | hssi_diffio
pma_rx_buf_xrx_path_datarate | 10800000000 bps
pma_rx_buf_xrx_path_datawidth | 64
pma_rx_buf_xrx_path_pma_rx_divclk_hz | 168750000
pma_rx_buf_xrx_path_optimal | true
pma_rx_buf_link | sr
pma_rx_buf_xrx_path_initial_settings | true
pma_rx_buf_rx_vga_oc_en | vga_cal_off
pma_rx_sd_silicon_rev | 20nm5es
pma_rx_sd_link | sr
pma_rx_sd_optimal | true
pma_rx_sd_power_mode | mid_power
pma_rx_sd_prot_mode | basic_rx
pma_rx_sd_sd_output_off | 1
pma_rx_sd_sd_output_on | 15
pma_rx_sd_sd_pdb | sd_off
pma_rx_sd_sd_threshold | sdlv_3
pma_rx_sd_sup_mode | user_mode
pma_tx_ser_silicon_rev | 20nm5es
pma_tx_ser_clk_divtx_deskew | deskew_delay8
pma_tx_ser_control_clk_divtx | no_dft_control_clkdivtx
pma_tx_ser_duty_cycle_correction_mode_ctrl | dcc_disable
pma_tx_ser_ser_clk_divtx_user_sel | divtx_user_33
pma_tx_ser_ser_clk_mon | disable_clk_mon
pma_tx_ser_ser_powerdown | normal_poweron_ser
pma_tx_ser_sup_mode | user_mode
pma_tx_ser_initial_settings | true
pma_tx_ser_prot_mode | basic_tx
pma_tx_ser_bonding_mode | x1_non_bonded
pma_tx_buf_silicon_rev | 20nm5es
pma_tx_buf_datarate | 10800000000 bps
pma_tx_buf_dft_sel | dft_disabled
pma_tx_buf_duty_cycle_correction_bandwidth | dcc_bw_12
pma_tx_buf_duty_cycle_correction_mode_ctrl | dcc_disable
pma_tx_buf_duty_cycle_input_polarity | dcc_input_pos
pma_tx_buf_duty_cycle_setting | dcc_t32
pma_tx_buf_duty_cycle_setting_aux | dcc2_t32
pma_tx_buf_jtag_drv_sel | drv1
pma_tx_buf_jtag_lp | lp_off
pma_tx_buf_link_tx | sr
pma_tx_buf_lst | atb_disabled
pma_tx_buf_optimal | true
pma_tx_buf_pre_emp_sign_1st_post_tap | fir_post_1t_neg
pma_tx_buf_pre_emp_sign_2nd_post_tap | fir_post_2t_neg
pma_tx_buf_pre_emp_sign_pre_tap_1t | fir_pre_1t_neg
pma_tx_buf_pre_emp_sign_pre_tap_2t | fir_pre_2t_neg
pma_tx_buf_pre_emp_switching_ctrl_1st_post_tap | 0
pma_tx_buf_pre_emp_switching_ctrl_2nd_post_tap | 0
pma_tx_buf_pre_emp_switching_ctrl_pre_tap_1t | 0
pma_tx_buf_pre_emp_switching_ctrl_pre_tap_2t | 0
pma_tx_buf_prot_mode | basic_tx
pma_tx_buf_rx_det | mode_0
pma_tx_buf_rx_det_output_sel | rx_det_pcie_out
pma_tx_buf_rx_det_pdb | rx_det_off
pma_tx_buf_slew_rate_ctrl | slew_r5
pma_tx_buf_sup_mode | user_mode
pma_tx_buf_term_code | rterm_code7
pma_tx_buf_term_sel | r_r1
pma_tx_buf_tx_powerdown | normal_tx_on
pma_tx_buf_user_fir_coeff_ctrl_sel | ram_ctl
pma_tx_buf_vod_output_swing_ctrl | 31
pma_tx_buf_initial_settings | true
pma_tx_buf_duty_cycle_correction_reference2 | dcc_ref2_3
pma_tx_buf_ser_powerdown | normal_ser_on
pma_tx_buf_swing_level | lv
pma_tx_buf_vreg_output | vccdreg_nominal
pma_tx_buf_duty_cycle_correction_reference1 | dcc_ref1_3
pma_tx_buf_duty_cycle_correction_reset_n | reset_n
pma_tx_buf_res_cal_local | non_local
pma_tx_buf_term_n_tune | rterm_n0
pma_tx_buf_cpen_ctrl | cp_l0
pma_tx_buf_term_p_tune | rterm_p0
pma_tx_buf_calibration_en | false
pma_tx_buf_low_power_en | disable
pma_tx_buf_compensation_en | enable
pma_tx_buf_dcd_detection_en | enable
pma_tx_buf_uc_txvod_cal | uc_tx_vod_cal_off
pma_tx_buf_uc_txvod_cal_cont | uc_tx_vod_cal_cont_off
pma_tx_buf_uc_skew_cal | uc_skew_cal_off
pma_tx_buf_uc_dcd_cal | uc_dcd_cal_off
pma_tx_buf_uc_txvod_cal_status | uc_tx_vod_cal_notdone
pma_tx_buf_uc_skew_cal_status | uc_skew_cal_notdone
pma_tx_buf_uc_dcd_cal_status | uc_dcd_cal_notdone
pma_tx_buf_uc_gen3 | gen3_off
pma_tx_buf_uc_gen4 | gen4_off
pma_tx_buf_uc_vcc_setting | vcc_setting1
pma_tx_buf_mcgb_location_for_pcie | 0
pma_tx_buf_xtx_path_prot_mode | basic_tx
pma_tx_buf_xtx_path_optimal | true
pma_tx_buf_xtx_path_datarate | 10800000000 bps
pma_tx_buf_xtx_path_datawidth | 64
pma_tx_buf_xtx_path_clock_divider_ratio | 1
pma_tx_buf_xtx_path_pma_tx_divclk_hz | 168750000
pma_tx_buf_xtx_path_tx_pll_clk_hz | 5400000000
pma_tx_buf_link | sr
pma_tx_buf_xtx_path_swing_level | lv
pma_tx_buf_xtx_path_sup_mode | user_mode
pma_tx_buf_xtx_path_initial_settings | true
pma_tx_buf_xtx_path_calibration_en | false
pma_tx_buf_xtx_path_bonding_mode | x1_non_bonded
pma_tx_buf_pm_speed_grade | e2
pma_tx_buf_power_mode | mid_power
pma_tx_buf_power_rail_et | 1030
pma_tx_buf_power_rail_eht | 0
pma_tx_buf_xtx_path_gt_enabled | disable
pma_tx_buf_xtx_path_analog_mode | user_custom
pma_tx_buf_compensation_driver_en | disable
pma_tx_buf_sense_amp_offset_cal_curr_p | 0
pma_tx_buf_chgpmp_current_dn_trim | cp_current_trimming_dn_setting0
pma_tx_buf_duty_cycle_correction_bandwidth_dn | dcd_bw_dn_0
pma_tx_buf_sense_amp_offset_cal_curr_n | sa_os_cal_in_0
pma_tx_buf_chgpmp_current_up_trim | cp_current_trimming_up_setting0
pma_tx_buf_chgpmp_up_trim_double | normal_up_trim_current
pma_tx_buf_duty_cycle_cp_comp_en | cp_comp_off
pma_tx_buf_dcd_clk_div_ctrl | dcd_ck_div128
pma_tx_buf_duty_cycle_detector_sa_cal | dcd_sa_cal_disable
pma_tx_buf_duty_cycle_detector_cp_cal | dcd_cp_cal_disable
pma_tx_buf_tri_driver | tri_driver_disable
pma_tx_buf_cdr_cp_calibration_en | cdr_cp_cal_disable
pma_tx_buf_chgpmp_dn_trim_double | normal_dn_trim_current
pma_tx_buf_calibration_resistor_value | res_setting0
pma_tx_buf_enable_idle_tx_channel_support | false
cdr_pll_silicon_rev | 20nm5es
cdr_pll_pma_width | 64
cdr_pll_cgb_div | 1
cdr_pll_is_cascaded_pll | false
cdr_pll_bandwidth_range_high | 0 hz
cdr_pll_bandwidth_range_low | 0 hz
cdr_pll_datarate | 10800000000 bps
cdr_pll_f_max_pfd | 350000000 Hz
cdr_pll_f_max_ref | 800000000 Hz
cdr_pll_f_max_vco | 9800000000 Hz
cdr_pll_f_min_gt_channel | 8700000000 Hz
cdr_pll_f_min_pfd | 50000000 Hz
cdr_pll_f_min_ref | 50000000 Hz
cdr_pll_f_min_vco | 4900000000 Hz
cdr_pll_lpd_counter | 1
cdr_pll_lpfd_counter | 2
cdr_pll_n_counter_scratch | 1
cdr_pll_output_clock_frequency | 5400000000 Hz
cdr_pll_reference_clock_frequency | 270000000 hz
cdr_pll_set_cdr_vco_speed | 3
cdr_pll_set_cdr_vco_speed_fix | 60
cdr_pll_vco_freq | 5400000000 Hz
cdr_pll_atb_select_control | atb_off
cdr_pll_auto_reset_on | auto_reset_off
cdr_pll_bbpd_data_pattern_filter_select | bbpd_data_pat_off
cdr_pll_bw_sel | medium
cdr_pll_cdr_odi_select | sel_cdr
cdr_pll_cdr_phaselock_mode | no_ignore_lock
cdr_pll_cdr_powerdown_mode | power_up
cdr_pll_chgpmp_current_pd | cp_current_pd_setting0
cdr_pll_chgpmp_current_pfd | cp_current_pfd_setting2
cdr_pll_chgpmp_replicate | false
cdr_pll_chgpmp_testmode | cp_test_disable
cdr_pll_clklow_mux_select | clklow_mux_cdr_fbclk
cdr_pll_diag_loopback_enable | false
cdr_pll_disable_up_dn | true
cdr_pll_fref_clklow_div | 1
cdr_pll_fref_mux_select | fref_mux_cdr_refclk
cdr_pll_gpon_lck2ref_control | gpon_lck2ref_off
cdr_pll_initial_settings | true
cdr_pll_lck2ref_delay_control | lck2ref_delay_2
cdr_pll_lf_resistor_pd | lf_pd_setting2
cdr_pll_lf_resistor_pfd | lf_pfd_setting2
cdr_pll_lf_ripple_cap | lf_no_ripple
cdr_pll_loop_filter_bias_select | lpflt_bias_7
cdr_pll_loopback_mode | loopback_disabled
cdr_pll_ltd_ltr_micro_controller_select | ltd_ltr_pcs
cdr_pll_m_counter | 10
cdr_pll_n_counter | 1
cdr_pll_optimal | true
cdr_pll_pd_fastlock_mode | false
cdr_pll_pd_l_counter | 1
cdr_pll_pfd_l_counter | 2
cdr_pll_position | position_unknown
cdr_pll_power_mode | mid_power
cdr_pll_primary_use | cdr
cdr_pll_prot_mode | basic_rx
cdr_pll_requires_gt_capable_channel | false
cdr_pll_reverse_serial_loopback | no_loopback
cdr_pll_set_cdr_v2i_enable | true
cdr_pll_set_cdr_vco_reset | false
cdr_pll_set_cdr_vco_speed_pciegen3 | cdr_vco_max_speedbin_pciegen3
cdr_pll_side | side_unknown
cdr_pll_pm_speed_grade | e2
cdr_pll_sup_mode | user_mode
cdr_pll_top_or_bottom | tb_unknown
cdr_pll_tx_pll_prot_mode | txpll_unused
cdr_pll_txpll_hclk_driver_enable | false
cdr_pll_vco_overrange_voltage | vco_overrange_off
cdr_pll_vco_underrange_voltage | vco_underange_off
cdr_pll_fb_select | direct_fb
cdr_pll_uc_ro_cal | uc_ro_cal_on
cdr_pll_uc_ro_cal_status | uc_ro_cal_notdone
cdr_pll_iqclk_mux_sel | power_down
cdr_pll_uc_cru_rstb | cdr_lf_reset_off
cdr_pll_pcie_gen | non_pcie
cdr_pll_analog_mode | user_custom
cdr_pll_f_max_m_counter | 1
cdr_pll_chgpmp_vccreg | vreg_fw0
cdr_pll_set_cdr_input_freq_range | 0
cdr_pll_chgpmp_current_dn_trim | cp_current_trimming_dn_setting0
cdr_pll_chgpmp_up_pd_trim_double | normal_up_trim_current
cdr_pll_chgpmp_current_up_pd | cp_current_pd_up_setting3
cdr_pll_f_max_cmu_out_freq | 1
cdr_pll_chgpmp_current_up_trim | cp_current_trimming_up_setting0
cdr_pll_chgpmp_dn_pd_trim_double | normal_dn_trim_current
cdr_pll_cal_vco_count_length | sel_8b_count
cdr_pll_chgpmp_current_dn_pd | cp_current_pd_dn_setting3
cdr_pll_enable_idle_rx_channel_support | false
pma_rx_deser_silicon_rev | 20nm5es
pma_rx_deser_clkdiv_source | vco_bypass_normal
pma_rx_deser_clkdivrx_user_mode | clkdivrx_user_div33
pma_rx_deser_datarate | 10800000000 bps
pma_rx_deser_deser_factor | 64
pma_rx_deser_deser_powerdown | deser_power_up
pma_rx_deser_force_adaptation_outputs | normal_outputs
pma_rx_deser_force_clkdiv_for_testing | normal_clkdiv
pma_rx_deser_optimal | true
pma_rx_deser_sdclk_enable | false
pma_rx_deser_sup_mode | user_mode
pma_rx_deser_rst_n_adapt_odi | no_rst_adapt_odi
pma_rx_deser_bitslip_bypass | bs_bypass_yes
pma_rx_deser_prot_mode | basic_rx
pma_rx_deser_pcie_gen | non_pcie
pma_rx_deser_pcie_gen_bitwidth | pcie_gen3_32b
pma_rx_deser_tdr_mode | select_bbpd_data
data_rate_bps | 10800000000 bps
l_protocol_mode | teng_baser_mode
pcs_speedgrade | e3
pma_speedgrade | e2
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## xcvr_reset_control_0

altera_xcvr_reset_control v17.1

clk_0 | clk | xcvr_reset_control_0
clock
clk_reset
reset
xcvr_native_a10_0 | tx_digitalreset
tx_digitalreset
|  | rx_analogreset | xcvr_native_a10_0
|  | rx_analogreset
|  | rx_cal_busy
|  | rx_cal_busy
|  | rx_digitalreset
|  | rx_digitalreset
|  | rx_is_lockedtodata
|  | rx_is_lockedtodata
|  | tx_analogreset
|  | tx_analogreset
|  | tx_cal_busy
|  | tx_cal_busy

## Parameters
device_family | ARRIA10
CHANNELS | 1
PLLS | 1
SYS_CLK_IN_MHZ | 125
SYNCHRONIZE_RESET | 1
REDUCED_SIM_TIME | 1
gui_split_interfaces | 0
TX_PLL_ENABLE | 0
T_PLL_POWERDOWN | 1000
SYNCHRONIZE_PLL_RESET | 0
TX_ENABLE | 1
TX_PER_CHANNEL | 0
gui_tx_auto_reset | 0
T_TX_ANALOGRESET | 70000
T_TX_DIGITALRESET | 70000
T_PLL_LOCK_HYST | 0
gui_pll_cal_busy | 0
EN_PLL_CAL_BUSY | 0
RX_ENABLE | 1
RX_PER_CHANNEL | 0
gui_rx_auto_reset | 0
T_RX_ANALOGRESET | 70000
T_RX_DIGITALRESET | 4000
l_terminate_pll | 1
l_terminate_tx | 0
l_terminate_rx | 0
l_terminate_tx_manual | 1
l_terminate_rx_manual | 1
l_tx_manual_term | 0
l_rx_manual_term | 0
l_pll_select_split | 0
l_pll_select_width | 1
l_pll_select_base | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

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