control |

2018.05.01.09:18:29 | Datasheet

Overview

clk | control

Processor
nios2_gen2_0 Nios II 17.1
All Components
control_reg altera_avalon_pio 17.1
data_pattern_checker_0 altera_avalon_data_pattern_checker 17.1
data_pattern_checker_1 altera_avalon_data_pattern_checker 17.1
data_pattern_checker_10 altera_avalon_data_pattern_checker 17.1
data_pattern_checker_2 altera_avalon_data_pattern_checker 17.1
data_pattern_checker_3 altera_avalon_data_pattern_checker 17.1
data_pattern_checker_4 altera_avalon_data_pattern_checker 17.1
data_pattern_checker_5 altera_avalon_data_pattern_checker 17.1
data_pattern_checker_6 altera_avalon_data_pattern_checker 17.1
data_pattern_checker_7 altera_avalon_data_pattern_checker 17.1
data_pattern_checker_8 altera_avalon_data_pattern_checker 17.1
data_pattern_checker_9 altera_avalon_data_pattern_checker 17.1
data_pattern_generator_0 altera_avalon_data_pattern_generator 17.1
data_pattern_generator_1 altera_avalon_data_pattern_generator 17.1
data_pattern_generator_10 altera_avalon_data_pattern_generator 17.1
data_pattern_generator_2 altera_avalon_data_pattern_generator 17.1
data_pattern_generator_3 altera_avalon_data_pattern_generator 17.1
data_pattern_generator_4 altera_avalon_data_pattern_generator 17.1
data_pattern_generator_5 altera_avalon_data_pattern_generator 17.1
data_pattern_generator_6 altera_avalon_data_pattern_generator 17.1
data_pattern_generator_7 altera_avalon_data_pattern_generator 17.1
data_pattern_generator_8 altera_avalon_data_pattern_generator 17.1
data_pattern_generator_9 altera_avalon_data_pattern_generator 17.1
irq_10us altera_avalon_timer 17.1
nios2_gen2_0 altera_nios2_gen2 17.1
onchip_memory2_0 altera_avalon_onchip_memory2 17.1
sys_clk_timer altera_avalon_timer 17.1
uart_0 altera_avalon_uart 17.1
Memory Map

| nios2_gen2_0
data_master | instruction_master
control_reg |  |
s1 | 0x00003000 |
data_pattern_checker_0 |  |
csr_slave | 0x00005000 |
data_pattern_checker_1 |  |
csr_slave | 0x00007000 |
data_pattern_checker_10 |  |
csr_slave | 0x00019000 |
data_pattern_checker_2 |  |
csr_slave | 0x00009000 |
data_pattern_checker_3 |  |
csr_slave | 0x0000b000 |
data_pattern_checker_4 |  |
csr_slave | 0x0000d000 |
data_pattern_checker_5 |  |
csr_slave | 0x0000f000 |
data_pattern_checker_6 |  |
csr_slave | 0x00011000 |
data_pattern_checker_7 |  |
csr_slave | 0x00013000 |
data_pattern_checker_8 |  |
csr_slave | 0x00015000 |
data_pattern_checker_9 |  |
csr_slave | 0x00017000 |
data_pattern_generator_0 |  |
csr_slave | 0x00004000 |
data_pattern_generator_1 |  |
csr_slave | 0x00006000 |
data_pattern_generator_10 |  |
csr_slave | 0x00018000 |
data_pattern_generator_2 |  |
csr_slave | 0x00008000 |
data_pattern_generator_3 |  |
csr_slave | 0x0000a000 |
data_pattern_generator_4 |  |
csr_slave | 0x0000c000 |
data_pattern_generator_5 |  |
csr_slave | 0x0000e000 |
data_pattern_generator_6 |  |
csr_slave | 0x00010000 |
data_pattern_generator_7 |  |
csr_slave | 0x00012000 |
data_pattern_generator_8 |  |
csr_slave | 0x00014000 |
data_pattern_generator_9 |  |
csr_slave | 0x00016000 |
irq_10us |  |
s1 | 0x00001000 |
nios2_gen2_0 |  |
debug_mem_slave | 0x00040800 | 0x00040800
onchip_memory2_0 |  |
s1 | 0x10000000 | 0x10000000
sys_clk_timer |  |
s1 | 0x00002000 |
uart_0 |  |
s1 | 0x00041000 |

## clk

clock_source v17.1

## Parameters
clockFrequency | 100000000
clockFrequencyKnown | true
inputClockFrequency | 0
resetSynchronousEdges | NONE
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## control_reg

altera_avalon_pio v17.1

nios2_gen2_0 | data_master | control_reg
s1
clk | clk
clk
clk_reset
reset

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 32
clockRate | 100000000
derived_has_tri | false
derived_has_out | true
derived_has_in | false
derived_do_test_bench_wiring | false
derived_capture | false
derived_edge_type | NONE
derived_irq_type | NONE
derived_has_irq | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 32
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 100000000
HAS_IN | 0
HAS_OUT | 1
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 0

## data_pattern_checker_0

altera_avalon_data_pattern_checker v17.1

nios2_gen2_0 | data_master | data_pattern_checker_0
csr_slave
clk | clk
csr_clk
clk_reset
reset

## Parameters
ST_DATA_W | 64
NUM_CYCLES_FOR_LOCK | 40
BYPASS_ENABLED | false
AVALON_ENABLED | true
FREQ_CNTER_ENABLED | false
CROSS_CLK_SYNC_DEPTH | 2
AUTO_DEVICE_FAMILY | ARRIA10
AUTO_DEVICE | 10AX090N2F40E2SG
AUTO_DEVICE_SPEEDGRADE | 2
AUTO_CSR_CLK_CLOCK_RATE | 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN | 1
AUTO_CSR_CLK_RESET_DOMAIN | 1
deviceFamily | Arria 10
generateLegacySim | false

## Software Assignments (none)

## data_pattern_checker_1

altera_avalon_data_pattern_checker v17.1

nios2_gen2_0 | data_master | data_pattern_checker_1
csr_slave
clk | clk
csr_clk
clk_reset
reset

## Parameters
ST_DATA_W | 64
NUM_CYCLES_FOR_LOCK | 40
BYPASS_ENABLED | false
AVALON_ENABLED | true
FREQ_CNTER_ENABLED | false
CROSS_CLK_SYNC_DEPTH | 2
AUTO_DEVICE_FAMILY | ARRIA10
AUTO_DEVICE | 10AX090N2F40E2SG
AUTO_DEVICE_SPEEDGRADE | 2
AUTO_CSR_CLK_CLOCK_RATE | 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN | 1
AUTO_CSR_CLK_RESET_DOMAIN | 1
deviceFamily | Arria 10
generateLegacySim | false

## Software Assignments (none)

## data_pattern_checker_10

altera_avalon_data_pattern_checker v17.1

nios2_gen2_0 | data_master | data_pattern_checker_10
csr_slave
clk | clk
csr_clk
clk_reset
reset

## Parameters
ST_DATA_W | 64
NUM_CYCLES_FOR_LOCK | 40
BYPASS_ENABLED | false
AVALON_ENABLED | true
FREQ_CNTER_ENABLED | false
CROSS_CLK_SYNC_DEPTH | 2
AUTO_DEVICE_FAMILY | ARRIA10
AUTO_DEVICE | 10AX090N2F40E2SG
AUTO_DEVICE_SPEEDGRADE | 2
AUTO_CSR_CLK_CLOCK_RATE | 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN | 1
AUTO_CSR_CLK_RESET_DOMAIN | 1
deviceFamily | Arria 10
generateLegacySim | false

## Software Assignments (none)

## data_pattern_checker_2

altera_avalon_data_pattern_checker v17.1

nios2_gen2_0 | data_master | data_pattern_checker_2
csr_slave
clk | clk
csr_clk
clk_reset
reset

## Parameters
ST_DATA_W | 64
NUM_CYCLES_FOR_LOCK | 40
BYPASS_ENABLED | false
AVALON_ENABLED | true
FREQ_CNTER_ENABLED | false
CROSS_CLK_SYNC_DEPTH | 2
AUTO_DEVICE_FAMILY | ARRIA10
AUTO_DEVICE | 10AX090N2F40E2SG
AUTO_DEVICE_SPEEDGRADE | 2
AUTO_CSR_CLK_CLOCK_RATE | 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN | 1
AUTO_CSR_CLK_RESET_DOMAIN | 1
deviceFamily | Arria 10
generateLegacySim | false

## Software Assignments (none)

## data_pattern_checker_3

altera_avalon_data_pattern_checker v17.1

nios2_gen2_0 | data_master | data_pattern_checker_3
csr_slave
clk | clk
csr_clk
clk_reset
reset

## Parameters
ST_DATA_W | 64
NUM_CYCLES_FOR_LOCK | 40
BYPASS_ENABLED | false
AVALON_ENABLED | true
FREQ_CNTER_ENABLED | false
CROSS_CLK_SYNC_DEPTH | 2
AUTO_DEVICE_FAMILY | ARRIA10
AUTO_DEVICE | 10AX090N2F40E2SG
AUTO_DEVICE_SPEEDGRADE | 2
AUTO_CSR_CLK_CLOCK_RATE | 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN | 1
AUTO_CSR_CLK_RESET_DOMAIN | 1
deviceFamily | Arria 10
generateLegacySim | false

## Software Assignments (none)

## data_pattern_checker_4

altera_avalon_data_pattern_checker v17.1

nios2_gen2_0 | data_master | data_pattern_checker_4
csr_slave
clk | clk
csr_clk
clk_reset
reset

## Parameters
ST_DATA_W | 64
NUM_CYCLES_FOR_LOCK | 40
BYPASS_ENABLED | false
AVALON_ENABLED | true
FREQ_CNTER_ENABLED | false
CROSS_CLK_SYNC_DEPTH | 2
AUTO_DEVICE_FAMILY | ARRIA10
AUTO_DEVICE | 10AX090N2F40E2SG
AUTO_DEVICE_SPEEDGRADE | 2
AUTO_CSR_CLK_CLOCK_RATE | 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN | 1
AUTO_CSR_CLK_RESET_DOMAIN | 1
deviceFamily | Arria 10
generateLegacySim | false

## Software Assignments (none)

## data_pattern_checker_5

altera_avalon_data_pattern_checker v17.1

nios2_gen2_0 | data_master | data_pattern_checker_5
csr_slave
clk | clk
csr_clk
clk_reset
reset

## Parameters
ST_DATA_W | 64
NUM_CYCLES_FOR_LOCK | 40
BYPASS_ENABLED | false
AVALON_ENABLED | true
FREQ_CNTER_ENABLED | false
CROSS_CLK_SYNC_DEPTH | 2
AUTO_DEVICE_FAMILY | ARRIA10
AUTO_DEVICE | 10AX090N2F40E2SG
AUTO_DEVICE_SPEEDGRADE | 2
AUTO_CSR_CLK_CLOCK_RATE | 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN | 1
AUTO_CSR_CLK_RESET_DOMAIN | 1
deviceFamily | Arria 10
generateLegacySim | false

## Software Assignments (none)

## data_pattern_checker_6

altera_avalon_data_pattern_checker v17.1

nios2_gen2_0 | data_master | data_pattern_checker_6
csr_slave
clk | clk
csr_clk
clk_reset
reset

## Parameters
ST_DATA_W | 64
NUM_CYCLES_FOR_LOCK | 40
BYPASS_ENABLED | false
AVALON_ENABLED | true
FREQ_CNTER_ENABLED | false
CROSS_CLK_SYNC_DEPTH | 2
AUTO_DEVICE_FAMILY | ARRIA10
AUTO_DEVICE | 10AX090N2F40E2SG
AUTO_DEVICE_SPEEDGRADE | 2
AUTO_CSR_CLK_CLOCK_RATE | 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN | 1
AUTO_CSR_CLK_RESET_DOMAIN | 1
deviceFamily | Arria 10
generateLegacySim | false

## Software Assignments (none)

## data_pattern_checker_7

altera_avalon_data_pattern_checker v17.1

nios2_gen2_0 | data_master | data_pattern_checker_7
csr_slave
clk | clk
csr_clk
clk_reset
reset

## Parameters
ST_DATA_W | 64
NUM_CYCLES_FOR_LOCK | 40
BYPASS_ENABLED | false
AVALON_ENABLED | true
FREQ_CNTER_ENABLED | false
CROSS_CLK_SYNC_DEPTH | 2
AUTO_DEVICE_FAMILY | ARRIA10
AUTO_DEVICE | 10AX090N2F40E2SG
AUTO_DEVICE_SPEEDGRADE | 2
AUTO_CSR_CLK_CLOCK_RATE | 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN | 1
AUTO_CSR_CLK_RESET_DOMAIN | 1
deviceFamily | Arria 10
generateLegacySim | false

## Software Assignments (none)

## data_pattern_checker_8

altera_avalon_data_pattern_checker v17.1

nios2_gen2_0 | data_master | data_pattern_checker_8
csr_slave
clk | clk
csr_clk
clk_reset
reset

## Parameters
ST_DATA_W | 64
NUM_CYCLES_FOR_LOCK | 40
BYPASS_ENABLED | false
AVALON_ENABLED | true
FREQ_CNTER_ENABLED | false
CROSS_CLK_SYNC_DEPTH | 2
AUTO_DEVICE_FAMILY | ARRIA10
AUTO_DEVICE | 10AX090N2F40E2SG
AUTO_DEVICE_SPEEDGRADE | 2
AUTO_CSR_CLK_CLOCK_RATE | 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN | 1
AUTO_CSR_CLK_RESET_DOMAIN | 1
deviceFamily | Arria 10
generateLegacySim | false

## Software Assignments (none)

## data_pattern_checker_9

altera_avalon_data_pattern_checker v17.1

nios2_gen2_0 | data_master | data_pattern_checker_9
csr_slave
clk | clk
csr_clk
clk_reset
reset

## Parameters
ST_DATA_W | 64
NUM_CYCLES_FOR_LOCK | 40
BYPASS_ENABLED | false
AVALON_ENABLED | true
FREQ_CNTER_ENABLED | false
CROSS_CLK_SYNC_DEPTH | 2
AUTO_DEVICE_FAMILY | ARRIA10
AUTO_DEVICE | 10AX090N2F40E2SG
AUTO_DEVICE_SPEEDGRADE | 2
AUTO_CSR_CLK_CLOCK_RATE | 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN | 1
AUTO_CSR_CLK_RESET_DOMAIN | 1
deviceFamily | Arria 10
generateLegacySim | false

## Software Assignments (none)

## data_pattern_generator_0

altera_avalon_data_pattern_generator v17.1

nios2_gen2_0 | data_master | data_pattern_generator_0
csr_slave
clk | clk
csr_clk
clk_reset
reset

## Parameters
ST_DATA_W | 64
BYPASS_ENABLED | false
AVALON_ENABLED | true
FREQ_CNTER_ENABLED | false
CROSS_CLK_SYNC_DEPTH | 2
AUTO_DEVICE_FAMILY | ARRIA10
AUTO_DEVICE | 10AX090N2F40E2SG
AUTO_DEVICE_SPEEDGRADE | 2
AUTO_CSR_CLK_CLOCK_RATE | 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN | 1
AUTO_CSR_CLK_RESET_DOMAIN | 1
deviceFamily | Arria 10
generateLegacySim | false

## Software Assignments (none)

## data_pattern_generator_1

altera_avalon_data_pattern_generator v17.1

nios2_gen2_0 | data_master | data_pattern_generator_1
csr_slave
clk | clk
csr_clk
clk_reset
reset

## Parameters
ST_DATA_W | 64
BYPASS_ENABLED | false
AVALON_ENABLED | true
FREQ_CNTER_ENABLED | false
CROSS_CLK_SYNC_DEPTH | 2
AUTO_DEVICE_FAMILY | ARRIA10
AUTO_DEVICE | 10AX090N2F40E2SG
AUTO_DEVICE_SPEEDGRADE | 2
AUTO_CSR_CLK_CLOCK_RATE | 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN | 1
AUTO_CSR_CLK_RESET_DOMAIN | 1
deviceFamily | Arria 10
generateLegacySim | false

## Software Assignments (none)

## data_pattern_generator_10

altera_avalon_data_pattern_generator v17.1

nios2_gen2_0 | data_master | data_pattern_generator_10
csr_slave
clk | clk
csr_clk
clk_reset
reset

## Parameters
ST_DATA_W | 64
BYPASS_ENABLED | false
AVALON_ENABLED | true
FREQ_CNTER_ENABLED | false
CROSS_CLK_SYNC_DEPTH | 2
AUTO_DEVICE_FAMILY | ARRIA10
AUTO_DEVICE | 10AX090N2F40E2SG
AUTO_DEVICE_SPEEDGRADE | 2
AUTO_CSR_CLK_CLOCK_RATE | 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN | 1
AUTO_CSR_CLK_RESET_DOMAIN | 1
deviceFamily | Arria 10
generateLegacySim | false

## Software Assignments (none)

## data_pattern_generator_2

altera_avalon_data_pattern_generator v17.1

nios2_gen2_0 | data_master | data_pattern_generator_2
csr_slave
clk | clk
csr_clk
clk_reset
reset

## Parameters
ST_DATA_W | 64
BYPASS_ENABLED | false
AVALON_ENABLED | true
FREQ_CNTER_ENABLED | false
CROSS_CLK_SYNC_DEPTH | 2
AUTO_DEVICE_FAMILY | ARRIA10
AUTO_DEVICE | 10AX090N2F40E2SG
AUTO_DEVICE_SPEEDGRADE | 2
AUTO_CSR_CLK_CLOCK_RATE | 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN | 1
AUTO_CSR_CLK_RESET_DOMAIN | 1
deviceFamily | Arria 10
generateLegacySim | false

## Software Assignments (none)

## data_pattern_generator_3

altera_avalon_data_pattern_generator v17.1

nios2_gen2_0 | data_master | data_pattern_generator_3
csr_slave
clk | clk
csr_clk
clk_reset
reset

## Parameters
ST_DATA_W | 64
BYPASS_ENABLED | false
AVALON_ENABLED | true
FREQ_CNTER_ENABLED | false
CROSS_CLK_SYNC_DEPTH | 2
AUTO_DEVICE_FAMILY | ARRIA10
AUTO_DEVICE | 10AX090N2F40E2SG
AUTO_DEVICE_SPEEDGRADE | 2
AUTO_CSR_CLK_CLOCK_RATE | 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN | 1
AUTO_CSR_CLK_RESET_DOMAIN | 1
deviceFamily | Arria 10
generateLegacySim | false

## Software Assignments (none)

## data_pattern_generator_4

altera_avalon_data_pattern_generator v17.1

nios2_gen2_0 | data_master | data_pattern_generator_4
csr_slave
clk | clk
csr_clk
clk_reset
reset

## Parameters
ST_DATA_W | 64
BYPASS_ENABLED | false
AVALON_ENABLED | true
FREQ_CNTER_ENABLED | false
CROSS_CLK_SYNC_DEPTH | 2
AUTO_DEVICE_FAMILY | ARRIA10
AUTO_DEVICE | 10AX090N2F40E2SG
AUTO_DEVICE_SPEEDGRADE | 2
AUTO_CSR_CLK_CLOCK_RATE | 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN | 1
AUTO_CSR_CLK_RESET_DOMAIN | 1
deviceFamily | Arria 10
generateLegacySim | false

## Software Assignments (none)

## data_pattern_generator_5

altera_avalon_data_pattern_generator v17.1

nios2_gen2_0 | data_master | data_pattern_generator_5
csr_slave
clk | clk
csr_clk
clk_reset
reset

## Parameters
ST_DATA_W | 64
BYPASS_ENABLED | false
AVALON_ENABLED | true
FREQ_CNTER_ENABLED | false
CROSS_CLK_SYNC_DEPTH | 2
AUTO_DEVICE_FAMILY | ARRIA10
AUTO_DEVICE | 10AX090N2F40E2SG
AUTO_DEVICE_SPEEDGRADE | 2
AUTO_CSR_CLK_CLOCK_RATE | 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN | 1
AUTO_CSR_CLK_RESET_DOMAIN | 1
deviceFamily | Arria 10
generateLegacySim | false

## Software Assignments (none)

## data_pattern_generator_6

altera_avalon_data_pattern_generator v17.1

nios2_gen2_0 | data_master | data_pattern_generator_6
csr_slave
clk | clk
csr_clk
clk_reset
reset

## Parameters
ST_DATA_W | 64
BYPASS_ENABLED | false
AVALON_ENABLED | true
FREQ_CNTER_ENABLED | false
CROSS_CLK_SYNC_DEPTH | 2
AUTO_DEVICE_FAMILY | ARRIA10
AUTO_DEVICE | 10AX090N2F40E2SG
AUTO_DEVICE_SPEEDGRADE | 2
AUTO_CSR_CLK_CLOCK_RATE | 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN | 1
AUTO_CSR_CLK_RESET_DOMAIN | 1
deviceFamily | Arria 10
generateLegacySim | false

## Software Assignments (none)

## data_pattern_generator_7

altera_avalon_data_pattern_generator v17.1

nios2_gen2_0 | data_master | data_pattern_generator_7
csr_slave
clk | clk
csr_clk
clk_reset
reset

## Parameters
ST_DATA_W | 64
BYPASS_ENABLED | false
AVALON_ENABLED | true
FREQ_CNTER_ENABLED | false
CROSS_CLK_SYNC_DEPTH | 2
AUTO_DEVICE_FAMILY | ARRIA10
AUTO_DEVICE | 10AX090N2F40E2SG
AUTO_DEVICE_SPEEDGRADE | 2
AUTO_CSR_CLK_CLOCK_RATE | 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN | 1
AUTO_CSR_CLK_RESET_DOMAIN | 1
deviceFamily | Arria 10
generateLegacySim | false

## Software Assignments (none)

## data_pattern_generator_8

altera_avalon_data_pattern_generator v17.1

nios2_gen2_0 | data_master | data_pattern_generator_8
csr_slave
clk | clk
csr_clk
clk_reset
reset

## Parameters
ST_DATA_W | 64
BYPASS_ENABLED | false
AVALON_ENABLED | true
FREQ_CNTER_ENABLED | false
CROSS_CLK_SYNC_DEPTH | 2
AUTO_DEVICE_FAMILY | ARRIA10
AUTO_DEVICE | 10AX090N2F40E2SG
AUTO_DEVICE_SPEEDGRADE | 2
AUTO_CSR_CLK_CLOCK_RATE | 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN | 1
AUTO_CSR_CLK_RESET_DOMAIN | 1
deviceFamily | Arria 10
generateLegacySim | false

## Software Assignments (none)

## data_pattern_generator_9

altera_avalon_data_pattern_generator v17.1

nios2_gen2_0 | data_master | data_pattern_generator_9
csr_slave
clk | clk
csr_clk
clk_reset
reset

## Parameters
ST_DATA_W | 64
BYPASS_ENABLED | false
AVALON_ENABLED | true
FREQ_CNTER_ENABLED | false
CROSS_CLK_SYNC_DEPTH | 2
AUTO_DEVICE_FAMILY | ARRIA10
AUTO_DEVICE | 10AX090N2F40E2SG
AUTO_DEVICE_SPEEDGRADE | 2
AUTO_CSR_CLK_CLOCK_RATE | 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN | 1
AUTO_CSR_CLK_RESET_DOMAIN | 1
deviceFamily | Arria 10
generateLegacySim | false

## Software Assignments (none)

## irq_10us

altera_avalon_timer v17.1

nios2_gen2_0 | data_master | irq_10us
s1
irq
irq
clk | clk
clk
clk_reset
reset

## Parameters
alwaysRun | false
counterSize | 32
fixedPeriod | false
period | 10
periodUnits | USEC
resetOutput | false
snapshot | true
timeoutPulseOutput | false
systemFrequency | 100000000
watchdogPulse | 2
timerPreset | FULL_FEATURED
periodUnitsString | us
valueInSecond | 1.0E-6
loadValue | 999
mult | 1.0E-6
ticksPerSec | 100000.0
slave_address_width | 3
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
ALWAYS_RUN | 0
COUNTER_SIZE | 32
FIXED_PERIOD | 0
FREQ | 100000000
LOAD_VALUE | 999
MULT | 0.000001
PERIOD | 10
PERIOD_UNITS | us
RESET_OUTPUT | 0
SNAPSHOT | 1
TICKS_PER_SEC | 100000
TIMEOUT_PULSE_OUTPUT | 0

## nios2_gen2_0

altera_nios2_gen2 v17.1

clk | clk | nios2_gen2_0
clk
clk_reset
reset
|  | data_master | data_pattern_generator_0
|  | csr_slave
|  | data_master | data_pattern_checker_0
|  | csr_slave
|  | data_master | data_pattern_generator_1
|  | csr_slave
|  | data_master | data_pattern_checker_1
|  | csr_slave
|  | data_master | data_pattern_generator_2
|  | csr_slave
|  | data_master | data_pattern_checker_2
|  | csr_slave
|  | data_master | data_pattern_generator_3
|  | csr_slave
|  | data_master | data_pattern_checker_3
|  | csr_slave
|  | data_master | data_pattern_generator_4
|  | csr_slave
|  | data_master | data_pattern_checker_4
|  | csr_slave
|  | data_master | data_pattern_generator_5
|  | csr_slave
|  | data_master | data_pattern_checker_5
|  | csr_slave
|  | data_master | data_pattern_generator_6
|  | csr_slave
|  | data_master | data_pattern_checker_6
|  | csr_slave
|  | data_master | data_pattern_generator_7
|  | csr_slave
|  | data_master | data_pattern_checker_7
|  | csr_slave
|  | data_master | data_pattern_generator_8
|  | csr_slave
|  | data_master | data_pattern_checker_8
|  | csr_slave
|  | data_master | data_pattern_generator_9
|  | csr_slave
|  | data_master | data_pattern_checker_9
|  | csr_slave
|  | data_master | data_pattern_generator_10
|  | csr_slave
|  | data_master | data_pattern_checker_10
|  | csr_slave
|  | data_master | onchip_memory2_0
|  | s1
|  | instruction_master
|  | s1
|  | data_master | irq_10us
|  | s1
|  | irq
|  | irq
|  | data_master | sys_clk_timer
|  | s1
|  | irq
|  | irq
|  | data_master | control_reg
|  | s1
|  | data_master | uart_0
|  | s1
|  | irq
|  | irq

## Parameters
tmr_enabled | false
setting_disable_tmr_inj | false
setting_showUnpublishedSettings | false
setting_showInternalSettings | false
setting_preciseIllegalMemAccessException | false
setting_exportPCB | false
setting_exportdebuginfo | false
setting_clearXBitsLDNonBypass | true
setting_bigEndian | false
setting_export_large_RAMs | false
setting_asic_enabled | false
register_file_por | false
setting_asic_synopsys_translate_on_off | false
setting_asic_third_party_synthesis | false
setting_asic_add_scan_mode_input | false
setting_oci_version | 1
setting_fast_register_read | false
setting_exportHostDebugPort | false
setting_oci_export_jtag_signals | false
setting_avalonDebugPortPresent | false
setting_alwaysEncrypt | true
io_regionbase | 0
io_regionsize | 0
setting_support31bitdcachebypass | true
setting_activateTrace | false
setting_allow_break_inst | false
setting_activateTestEndChecker | false
setting_ecc_sim_test_ports | false
setting_disableocitrace | false
setting_activateMonitors | true
setting_HDLSimCachesCleared | true
setting_HBreakTest | false
setting_breakslaveoveride | false
mpu_useLimit | false
mpu_enabled | false
mmu_enabled | false
mmu_autoAssignTlbPtrSz | true
cpuReset | false
resetrequest_enabled | true
setting_removeRAMinit | false
setting_tmr_output_disable | false
setting_shadowRegisterSets | 0
mpu_numOfInstRegion | 8
mpu_numOfDataRegion | 8
mmu_TLBMissExcOffset | 0
resetOffset | 0
exceptionOffset | 32
cpuID | 0
breakOffset | 32
userDefinedSettings |
tracefilename |
resetSlave | onchip_memory2_0.s1
mmu_TLBMissExcSlave | None
exceptionSlave | onchip_memory2_0.s1
breakSlave | None
setting_interruptControllerType | Internal
setting_branchpredictiontype | Dynamic
setting_bhtPtrSz | 8
cpuArchRev | 1
stratix_dspblock_shift_mul | false
shifterType | fast_le_shift
multiplierType | mul_fast32
mul_shift_choice | 0
mul_32_impl | 2
mul_64_impl | 0
shift_rot_impl | 1
dividerType | no_div
mpu_minInstRegionSize | 12
mpu_minDataRegionSize | 12
mmu_uitlbNumEntries | 4
mmu_udtlbNumEntries | 6
mmu_tlbPtrSz | 7
mmu_tlbNumWays | 16
mmu_processIDNumBits | 8
impl | Fast
icache_size | 4096
fa_cache_line | 2
fa_cache_linesize | 0
icache_tagramBlockType | Automatic
icache_ramBlockType | Automatic
icache_numTCIM | 0
icache_burstType | None
dcache_bursts | false
dcache_victim_buf_impl | ram
dcache_size | 2048
dcache_tagramBlockType | Automatic
dcache_ramBlockType | Automatic
dcache_numTCDM | 0
setting_exportvectors | false
setting_usedesignware | false
setting_ecc_present | false
setting_ic_ecc_present | true
setting_rf_ecc_present | true
setting_mmu_ecc_present | true
setting_dc_ecc_present | true
setting_itcm_ecc_present | true
setting_dtcm_ecc_present | true
regfile_ramBlockType | Automatic
ocimem_ramBlockType | Automatic
ocimem_ramInit | false
mmu_ramBlockType | Automatic
bht_ramBlockType | Automatic
cdx_enabled | false
mpx_enabled | false
debug_enabled | true
debug_triggerArming | true
debug_debugReqSignals | false
debug_assignJtagInstanceID | false
debug_jtagInstanceID | 0
debug_OCIOnchipTrace | _128
debug_hwbreakpoint | 0
debug_datatrigger | 0
debug_traceType | none
debug_traceStorage | onchip_trace
master_addr_map | false
instruction_master_paddr_base | 0
instruction_master_paddr_size | 0
flash_instruction_master_paddr_base | 0
flash_instruction_master_paddr_size | 0
data_master_paddr_base | 0
data_master_paddr_size | 0
tightly_coupled_instruction_master_0_paddr_base | 0
tightly_coupled_instruction_master_0_paddr_size | 0
tightly_coupled_instruction_master_1_paddr_base | 0
tightly_coupled_instruction_master_1_paddr_size | 0
tightly_coupled_instruction_master_2_paddr_base | 0
tightly_coupled_instruction_master_2_paddr_size | 0
tightly_coupled_instruction_master_3_paddr_base | 0
tightly_coupled_instruction_master_3_paddr_size | 0
tightly_coupled_data_master_0_paddr_base | 0
tightly_coupled_data_master_0_paddr_size | 0
tightly_coupled_data_master_1_paddr_base | 0
tightly_coupled_data_master_1_paddr_size | 0
tightly_coupled_data_master_2_paddr_base | 0
tightly_coupled_data_master_2_paddr_size | 0
tightly_coupled_data_master_3_paddr_base | 0
tightly_coupled_data_master_3_paddr_size | 0
instruction_master_high_performance_paddr_base | 0
instruction_master_high_performance_paddr_size | 0
data_master_high_performance_paddr_base | 0
data_master_high_performance_paddr_size | 0
resetAbsoluteAddr | 268435456
exceptionAbsoluteAddr | 268435488
breakAbsoluteAddr | 264224
mmu_TLBMissExcAbsAddr | 0
dcache_bursts_derived | false
dcache_size_derived | 2048
breakSlave_derived | nios2_gen2_0.debug_mem_slave
dcache_lineSize_derived | 32
setting_ioregionBypassDCache | false
setting_bit31BypassDCache | true
translate_on | "synthesis translate_on"
translate_off | "synthesis translate_off"
debug_onchiptrace | false
debug_offchiptrace | false
debug_insttrace | false
debug_datatrace | false
instAddrWidth | 29
faAddrWidth | 1
dataAddrWidth | 29
tightlyCoupledDataMaster0AddrWidth | 1
tightlyCoupledDataMaster1AddrWidth | 1
tightlyCoupledDataMaster2AddrWidth | 1
tightlyCoupledDataMaster3AddrWidth | 1
tightlyCoupledInstructionMaster0AddrWidth | 1
tightlyCoupledInstructionMaster1AddrWidth | 1
tightlyCoupledInstructionMaster2AddrWidth | 1
tightlyCoupledInstructionMaster3AddrWidth | 1
dataMasterHighPerformanceAddrWidth | 1
instructionMasterHighPerformanceAddrWidth | 1
instSlaveMapParam | <address-map><slave name='nios2_gen2_0.debug_mem_slave' start='0x40800' end='0x41000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='onchip_memory2_0.s1' start='0x10000000' end='0x10020000' type='altera_avalon_onchip_memory2.s1' /></address-map>
faSlaveMapParam |
dataSlaveMapParam | <address-map><slave name='irq_10us.s1' start='0x1000' end='0x1020' type='altera_avalon_timer.s1' /><slave name='sys_clk_timer.s1' start='0x2000' end='0x2020' type='altera_avalon_timer.s1' /><slave name='control_reg.s1' start='0x3000' end='0x3010' type='altera_avalon_pio.s1' /><slave name='data_pattern_generator_0.csr_slave' start='0x4000' end='0x4020' type='altera_avalon_data_pattern_generator.csr_slave' /><slave name='data_pattern_checker_0.csr_slave' start='0x5000' end='0x5020' type='altera_avalon_data_pattern_checker.csr_slave' /><slave name='data_pattern_generator_1.csr_slave' start='0x6000' end='0x6020' type='altera_avalon_data_pattern_generator.csr_slave' /><slave name='data_pattern_checker_1.csr_slave' start='0x7000' end='0x7020' type='altera_avalon_data_pattern_checker.csr_slave' /><slave name='data_pattern_generator_2.csr_slave' start='0x8000' end='0x8020' type='altera_avalon_data_pattern_generator.csr_slave' /><slave name='data_pattern_checker_2.csr_slave' start='0x9000' end='0x9020' type='altera_avalon_data_pattern_checker.csr_slave' /><slave name='data_pattern_generator_3.csr_slave' start='0xA000' end='0xA020' type='altera_avalon_data_pattern_generator.csr_slave' /><slave name='data_pattern_checker_3.csr_slave' start='0xB000' end='0xB020' type='altera_avalon_data_pattern_checker.csr_slave' /><slave name='data_pattern_generator_4.csr_slave' start='0xC000' end='0xC020' type='altera_avalon_data_pattern_generator.csr_slave' /><slave name='data_pattern_checker_4.csr_slave' start='0xD000' end='0xD020' type='altera_avalon_data_pattern_checker.csr_slave' /><slave name='data_pattern_generator_5.csr_slave' start='0xE000' end='0xE020' type='altera_avalon_data_pattern_generator.csr_slave' /><slave name='data_pattern_checker_5.csr_slave' start='0xF000' end='0xF020' type='altera_avalon_data_pattern_checker.csr_slave' /><slave name='data_pattern_generator_6.csr_slave' start='0x10000' end='0x10020' type='altera_avalon_data_pattern_generator.csr_slave' /><slave name='data_pattern_checker_6.csr_slave' start='0x11000' end='0x11020' type='altera_avalon_data_pattern_checker.csr_slave' /><slave name='data_pattern_generator_7.csr_slave' start='0x12000' end='0x12020' type='altera_avalon_data_pattern_generator.csr_slave' /><slave name='data_pattern_checker_7.csr_slave' start='0x13000' end='0x13020' type='altera_avalon_data_pattern_checker.csr_slave' /><slave name='data_pattern_generator_8.csr_slave' start='0x14000' end='0x14020' type='altera_avalon_data_pattern_generator.csr_slave' /><slave name='data_pattern_checker_8.csr_slave' start='0x15000' end='0x15020' type='altera_avalon_data_pattern_checker.csr_slave' /><slave name='data_pattern_generator_9.csr_slave' start='0x16000' end='0x16020' type='altera_avalon_data_pattern_generator.csr_slave' /><slave name='data_pattern_checker_9.csr_slave' start='0x17000' end='0x17020' type='altera_avalon_data_pattern_checker.csr_slave' /><slave name='data_pattern_generator_10.csr_slave' start='0x18000' end='0x18020' type='altera_avalon_data_pattern_generator.csr_slave' /><slave name='data_pattern_checker_10.csr_slave' start='0x19000' end='0x19020' type='altera_avalon_data_pattern_checker.csr_slave' /><slave name='nios2_gen2_0.debug_mem_slave' start='0x40800' end='0x41000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='uart_0.s1' start='0x41000' end='0x41020' type='altera_avalon_uart.s1' /><slave name='onchip_memory2_0.s1' start='0x10000000' end='0x10020000' type='altera_avalon_onchip_memory2.s1' /></address-map>
tightlyCoupledDataMaster0MapParam |
tightlyCoupledDataMaster1MapParam |
tightlyCoupledDataMaster2MapParam |
tightlyCoupledDataMaster3MapParam |
tightlyCoupledInstructionMaster0MapParam |
tightlyCoupledInstructionMaster1MapParam |
tightlyCoupledInstructionMaster2MapParam |
tightlyCoupledInstructionMaster3MapParam |
dataMasterHighPerformanceMapParam |
instructionMasterHighPerformanceMapParam |
clockFrequency | 100000000
deviceFamilyName | ARRIA10
internalIrqMaskSystemInfo | 7
customInstSlavesSystemInfo | <info/>
customInstSlavesSystemInfo_nios_a | <info/>
customInstSlavesSystemInfo_nios_b | <info/>
customInstSlavesSystemInfo_nios_c | <info/>
deviceFeaturesSystemInfo | ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0
AUTO_DEVICE | 10AX090N2F40E2SG
AUTO_DEVICE_SPEEDGRADE | 2
AUTO_CLK_CLOCK_DOMAIN | 1
AUTO_CLK_RESET_DOMAIN | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
BIG_ENDIAN | 0
BREAK_ADDR | 0x00040820
CPU_ARCH_NIOS2_R1 |
CPU_FREQ | 100000000u
CPU_ID_SIZE | 1
CPU_ID_VALUE | 0x00000000
CPU_IMPLEMENTATION | "fast"
DATA_ADDR_WIDTH | 29
DCACHE_BYPASS_MASK | 0x80000000
DCACHE_LINE_SIZE | 32
DCACHE_LINE_SIZE_LOG2 | 5
DCACHE_SIZE | 2048
EXCEPTION_ADDR | 0x10000020
FLASH_ACCELERATOR_LINES | 0
FLASH_ACCELERATOR_LINE_SIZE | 0
FLUSHDA_SUPPORTED |
HARDWARE_DIVIDE_PRESENT | 0
HARDWARE_MULTIPLY_PRESENT | 1
HARDWARE_MULX_PRESENT | 0
HAS_DEBUG_CORE | 1
HAS_DEBUG_STUB |
HAS_EXTRA_EXCEPTION_INFO |
HAS_ILLEGAL_INSTRUCTION_EXCEPTION |
HAS_JMPI_INSTRUCTION |
ICACHE_LINE_SIZE | 32
ICACHE_LINE_SIZE_LOG2 | 5
ICACHE_SIZE | 4096
INITDA_SUPPORTED |
INST_ADDR_WIDTH | 29
NUM_OF_SHADOW_REG_SETS | 0
OCI_VERSION | 1
RESET_ADDR | 0x10000000

## onchip_memory2_0

altera_avalon_onchip_memory2 v17.1

nios2_gen2_0 | data_master | onchip_memory2_0
s1
instruction_master
s1
clk | clk
clk1
clk_reset
reset1

## Parameters
allowInSystemMemoryContentEditor | false
blockType | AUTO
dataWidth | 32
dataWidth2 | 32
dualPort | false
enableDiffWidth | false
derived_enableDiffWidth | false
initMemContent | true
initializationFileName | onchip_mem.hex
enPRInitMode | false
instanceID | NONE
memorySize | 131072
readDuringWriteMode | DONT_CARE
simAllowMRAMContentsFile | false
simMemInitOnlyFilename | 0
singleClockOperation | false
derived_singleClockOperation | false
slave1Latency | 1
slave2Latency | 1
useNonDefaultInitFile | false
copyInitFile | false
useShallowMemBlocks | false
writable | true
ecc_enabled | false
resetrequest_enabled | true
autoInitializationFileName | control_onchip_memory2_0
deviceFamily | ARRIA10
deviceFeatures | ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0
derived_set_addr_width | 15
derived_set_addr_width2 | 15
derived_set_data_width | 32
derived_set_data_width2 | 32
derived_gui_ram_block_type | Automatic
derived_is_hardcopy | false
derived_init_file_name | control_onchip_memory2_0.hex
generateLegacySim | false

## Software Assignments
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR | 0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE | 0
CONTENTS_INFO | ""
DUAL_PORT | 0
GUI_RAM_BLOCK_TYPE | AUTO
INIT_CONTENTS_FILE | control_onchip_memory2_0
INIT_MEM_CONTENT | 1
INSTANCE_ID | NONE
NON_DEFAULT_INIT_FILE_ENABLED | 0
RAM_BLOCK_TYPE | AUTO
READ_DURING_WRITE_MODE | DONT_CARE
SINGLE_CLOCK_OP | 0
SIZE_MULTIPLE | 1
SIZE_VALUE | 131072
WRITABLE | 1

## sys_clk_timer

altera_avalon_timer v17.1

nios2_gen2_0 | data_master | sys_clk_timer
s1
irq
irq
clk | clk
clk
clk_reset
reset

## Parameters
alwaysRun | false
counterSize | 32
fixedPeriod | false
period | 1
periodUnits | MSEC
resetOutput | false
snapshot | true
timeoutPulseOutput | false
systemFrequency | 100000000
watchdogPulse | 2
timerPreset | FULL_FEATURED
periodUnitsString | ms
valueInSecond | 0.001
loadValue | 99999
mult | 0.001
ticksPerSec | 1000.0
slave_address_width | 3
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
ALWAYS_RUN | 0
COUNTER_SIZE | 32
FIXED_PERIOD | 0
FREQ | 100000000
LOAD_VALUE | 99999
MULT | 0.001
PERIOD | 1
PERIOD_UNITS | ms
RESET_OUTPUT | 0
SNAPSHOT | 1
TICKS_PER_SEC | 1000
TIMEOUT_PULSE_OUTPUT | 0

## uart_0

altera_avalon_uart v17.1

nios2_gen2_0 | data_master | uart_0
s1
irq
irq
clk | clk
clk
clk_reset
reset

## Parameters
baud | 115200
dataBits | 8
fixedBaud | true
parity | NONE
simCharStream |
simInteractiveInputEnable | false
simInteractiveOutputEnable | false
simTrueBaud | false
stopBits | 1
syncRegDepth | 2
useCtsRts | false
useEopRegister | false
useRelativePathForSimFile | false
clockRate | 100000000
baudError | 0.01
parityFisrtChar | N
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
BAUD | 115200
DATA_BITS | 8
FIXED_BAUD | 1
FREQ | 100000000
PARITY | 'N'
SIM_CHAR_STREAM | ""
SIM_TRUE_BAUD | 0
STOP_BITS | 1
SYNC_REG_DEPTH | 2
USE_CTS_RTS | 0
USE_EOP_REGISTER | 0

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