//file counter
//Auithor: @Tecstar from Macnica
//Rev.:    rev.1.0


module counter(scl_16cnt, wait_cnt,scl_en, wait_en, clk_div, rst);

//////////output////
output [4:0]scl_16cnt;
output [17:0]wait_cnt;

//////////input/////
input rst    ;
input clk_div;
input scl_en ;//SCLKを動かすステートenable信号 spi_state.vより
input wait_en;//WAITステートenable信号 spi_state.vより

//////////reg///////
reg [4:0]scl_16cnt;
reg [17:0]wait_cnt;

//////////wire//////

/////////parameter//
parameter S_CNT = 5'b11111;//16count
parameter W_CNT = 18'b111101000010010000;//250count,500ms
// 000000000011111010
// 111101000010010000
//111111011110101010

//////////assign_enable//////////////////////////


//////////SCL_16bits_counter////////////////////
always @ ( posedge clk_div or posedge rst ) begin
  if(rst == 1'b1) begin
      scl_16cnt <= 5'b00000;
  end
  else if (scl_16cnt == S_CNT)begin
      scl_16cnt <= 5'b00000;
  end//else
  else if (scl_en == 1'b1)begin
      scl_16cnt <= scl_16cnt + 1'b1;
  end//else
  else begin
  scl_16cnt <= 5'b00000;
  end
end//always


////////// Wait_counter////////////////////
always @ ( posedge clk_div or posedge rst ) begin
  if(rst == 1'b1) begin
      wait_cnt <= 18'b000000000000000000;
  end
  else if (wait_cnt == W_CNT)begin
      wait_cnt <= 18'b000000000000000000;
  end//else
  else if (wait_en == 1'b1)begin
      wait_cnt <= wait_cnt + 1'b1;
  end//else
  else begin
  wait_cnt <= 18'b000000000000000000;
  end
end//always
endmodule