`timescale 1ns/1ns

module testbench ();

	parameter cycle = 20;
	parameter half  = 10;

	reg				OSC_CLK;
	reg				RESET;
	reg				BUTTON;
	wire	[3:0]	LED;
	wire			moni_pllc0 = u1.pll_inst.c0;	
	wire	[31:0]	moni_cnt = u1.simple_counter_inst.counter_out;
	
	
	my_first_fpga u1 (
		.OSC_CLK	(OSC_CLK),
		.RESET		(RESET),
		.BUTTON		(BUTTON),
		.LED		(LED)
		);
	
	initial begin
		OSC_CLK <= 1'b0;
		RESET <= 1'b1;
		BUTTON <= 1'b1;		
		#(115000)
		RESET <= 1'b0;
		#(cycle * 30000)
		RESET <= 1'b1;		
		#(cycle * 10000000)
		BUTTON <= 1'b0;
		#(cycle * 5000000)
		BUTTON <= 1'b1;
	end
	
	always begin
		#(half) OSC_CLK <= ~OSC_CLK;
	end
endmodule