Connecting the Edge for a Sustainable Future Rules

All submitted projects must be based on the Cloud Connect Kit FPGA and fully used. The team includes products from Microsoft and Analog Devices, platform make full use of

■Technology provision(Until September 30, 2021)
- Project introduction and performance
- Block Diagram
- Expected sustainability results, projected resource savings

■technical paper(until February 7, 2022)
- Project introduction and performance (latest version)
- Block diagram (latest version)
- Description of FPGA benefits demonstrated in the project
・Performance improvement
・I/O expansion
・Adaptation to change
- Description of features and implementations
- performance metrics, expected performance
- Sustainability results, resource savings achieved
- Conclusion

■demonstration(Until February 7, 2021)
- Video demonstration of the design (maximum: 10 minutes)
- Upload it to the site and include the corresponding link in the technical paper
- Description of the design's design, functionality, and performance

■ Project source code (until February 7, 2022):
- Teams advancing to the Regional Finals must upload all project source code and
Need to share project link with contest organizer for judges to reference

■ Design concept: 30%
　 Creativity: 10%
Functionality: 10%
Sustainability effect: 10%

■ Implementation design: 30%
　 FPGA benefit from implementation: 20%
Use of 　contest platform (Analog Devices plug-in board, Microsoft Azure IoT): 10%

■ Design Performance: 40%
　 Proven technical performance and expectations: 10%
Sustainability impact, achieving significant resource savings: 10%
Hardware and software optimization: 20%

・All technical papers must be submitted in English, and Chinese teams should
Support in Chinese until the Grand Final held in English

・The team must be 3 people or less.

・All applicants must be 18 years or older

- You can only belong to one team

・Students can be supervised by a teacher or professor

・All entries must be submitted by the deadline
*We will not accept any extension of the deadline or delay in submission.

・When changing team members for any reason, the team needs approval from Terasic

・Existing designs can be submitted, but designs used in previous contests cannot be submitted.
And under no circumstances is the design permitted to be used commercially.
Entrants whose project appears to be a commercial product, those who have previously participated in other contests,
or disqualified if the submission to the previous contest is verified

・Each design must be created by the participants
Designs containing open source must clearly cite ownership and authorship
Designs containing third-party IP also require licensing

・The design can be changed until the examination date.
Latest version on Innovate FPGA site
Judging with proposed content, design and video

・By participating in the contest, Terasic and InnovateFPGA
Sponsors can use project information and related content for marketing purposes

- Use Terasic or the contest sponsor's logo in your team's design;
do not approve of these

If you have any questions regarding this contest, please contact us below.
Please refer to Terasic​ 's page for the official content of this cost test.