You will need to launch the Constraints Editor separately.

For further details, please refer to "10.2.4. Timing Analysis—Maximum Clock Frequency" in the "SmartTime Static Timing Analyzer User Guide".
Quote: "Restart the Libero Constraints Editor. The Constraints Editor must be running to use SmartTime's
back-annotation feature. Go to the Constraint Manager tab, then go to the Timing sub-tab, pull
down Edit with Constraint Editor, and choose Edit Timing Verification Constraints.”
https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/fpga/libero-software-later-versions#Documentation

example:

(1) In the Constraint Manager, open the Timing tab and then open Edit Timing Verification Constraints.

(2) When you open SmartTime using (1), you will be able to click Add Max Delay Constraint.

(3) The Constraints Editor will start, so enter the delay value etc. and apply it to the SDC file.