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Microchip FPGA: Where in the report can I find information on resource usage, such as FFs and LUTs?

Libero SoCs

Please refer to the <project name>_layout_log.log file located in Place and Route within the Reports window.

After logic synthesis and before placement and routing, the <project name>_compile_netlist_hier_resource.csv file is available as reference information within the Synthesize section of the Reports window.
The relevant CSV file is located at \<project folder>\designer\<project name>\<project name>_compile_netlist_hier_resources.csv.

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