Tools: SoC EDS


It seems that this is caused by the fact that the AXI bridge setting processing has not been performed. It can be solved by setting AXI bridge with one of the following.

・Set AXI bridge in Preloader.
・Set the AXI bridge in the user program. (Register direct control or use HWLib)

When using Preloader, it is possible to set the debugger script so that the AXI bridge setting process will work by executing the Preloader before running the Baremetal application. (For information on how to run the Preloader from a debugger script, please refer to the software sample provided with SoC EDS.)

If the user program supports it, the HWLib library installed with SoC EDS can be used.

Target APIs: alt_bridge_init, alt_addr_space_remap

The above API is used in the sample attached to SoC EDS, so please refer to it.

\embedded\examples\software\Altera-SoCFPGA-HardwareLib-FPGA-CV-GNU.tar.gz