I want to receive a clock in LVDS from a dedicated clock input pin in my Stratix V device. Does the FPGA have a built-in 100 Ω differential termination resistor on the dedicated clock input pin?

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I want to receive a clock over LVDS from a dedicated clock input pin on my Stratix V device.Is there a 100 Ω differential termination resistor on the dedicated clock input pin built into the FPGA?

Tools: Quartus® II
Device: Stratix® V
Category: Device (I/O)

In Stratix V devices, the dedicated clock input pins, like the I/O pins, have 100 Ω on-chip termination inside the FPGA and support True LVDS with on-chip termination (Rd). increase.

At that time, in the Assignment Editor,

To : <input pin>
Assignment Name : Input Termination
Value: Differential

Please compile with the following restrictions.
After compiling, check that Termination is Differential in Fitter ⇒ Resource Section ⇒ Input Pins in the compilation report.

For more information, please refer to the device handbook below.
https://www.altera.com/en_US/pdfs/literature/hb/stratix-v/stx5_core.pdf

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