The External Memory Interface Handbook released by Altera Corporation specifies a series termination resistance of 25 Ω when using SSTL Class II termination for pins intended for DDRx memory interfaces. If the characteristic impedance is 50Ω, how is impedance matching achieved?

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The External Memory Interface Handbook published by Altera specifies a series termination resistance value of 25Ω when using SSTL Class II termination for pins for DDRx memory interfaces. If the characteristic impedance is 50Ω, how is impedance matching achieved?

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SSTL Class II termination is intended for bidirectional signals, resulting in a circuit configuration with series/parallel termination. Transmitting impedance is 25Ω for the series termination plus about half of the 50Ω for the parallel termination for reception, which is 25Ω.

25Ω (series termination) + 25Ω (effect of parallel termination) = 50Ω

Impedance matching is achieved by the above image.
Note that the 25Ω series termination does not contribute to anti-reflection during reception, so you don't have to worry about it.

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