Category: SoCs


There are a total of three registers for the Altera SoC HPS GPIO, and they are allocated as shown below.

GPIO0 - GPIO muxes 0:28 - correspond to register bits 0:28
GPIO1 - GPIO muxes 29:57 - correspond to register bits 0:28
GPIO2 - GPIO muxes 58:70 - correspond to register bits 0:12
(NOTE: Cyclone V doesn't implement 67-70)
GPIO2 - GPI 0:13 - corresponds to bits 13:26
(These are the general purpose inputs in the SDRAM bank.)

Also, please note that the bit allocation is reversed for GPI, which is an input-only pin.
  https://www.altera.com/support/support-resources/knowledge-base/solutions/rd05162013_937.html