The output clock of the PLL in the Altera SoC's Hard Processor System (HPS) does not have the expected frequency. Please tell me what to do.

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The output clock of the PLL inside the Hard Processor System (HPS) of my Altera SoC is not at the expected frequency. Please tell me what to do.

SoC FPGAs

Target version: Quartus II v13.0 / v13.0SP1 / v13.1

The HPS input clock for Altera SoC comes from OSC1. However, if you use a clock other than 25MHz, the PLL division ratio set by the Preloader is incorrect and the expected frequency cannot be generated.

[Cause]
Because the input clock to OSC1 is fixed at 25MHz when generating Preloader.

【measures】
Please take one of the following measures.
・ Input 25MHz clock to OSC1
・ Modified Preloader source code

[How to modify Preloader]
Below is an example of modification when the input clock is 50MHz.

(after editing)
#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (31)
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (39)

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