In Qsys, does the vectored interrupt controller core (VIC) INT_ENABLE control register affect both maskable and non-maskable interrupts?
The INT_ENABLE control register of the vectored interrupt controller core (VIC) holds the enable state of each interrupt input.
Also, if the interrupt input for an interrupt that is not enabled is asserted, it is not considered by the priority processing block.
This applies to both maskable and non-maskable interrupts.
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