Is it possible to output a Verilog HDL testbench file when generating a CPRI core with Megawizard?

Output to a Verilog HDL file is not possible. VHDL only. There are also some restrictions on rates, options, devices, etc.

For details, refer to "CPRI MegaCore Function User Guide" (12.0), P.143 Running the Testbenches in the URL link below.
  https://www.altera.com/en_US/pdfs/literature/ug/ug_cpri.pdf