I want to implement a 1-lane PCI-Express interface using Arria II GX's PCI-Express hard IP, but can I only assign the TX and RX pins to channel 0 of the transceiver block?
I want to implement a 1-lane PCI-Express interface using Arria II GX's PCI-Express hard IP, but can I only assign the TX and RX pins to channel 0 of the transceiver block?
Yes, that's right.
For Arria II GX devices, the PCI-Express hard IP supports up to 8 lanes, so two transceiver blocks are supported (because each transceiver block has 4 lanes).
For example, if transceiver block 0 and transceiver block 1 support PCI-Express hard IP, only channel 0 of transceiver block 0 can be assigned to achieve 1 lane. Similarly, to achieve 4 lanes, it can be assigned to channels 0, 1, 2, and 3 of transceiver block 0. Therefore, use transceiver block 1 only when configuring 8 lanes.
In any case, when configuring the PCI-Express hard IP, it is recommended to create a sample design and check the pin assignment in advance.
Experienced FAE
Free consultation is available.
From specific product specifications to parts selection, the Company FAE will answer your technical concerns free of charge. Please feel free to contact us.