I'm considering PCI-Express interface for Altera's PCI-Express hard IP-equipped device. You can refer to how to build with Avalon-MM using Qsys on Altera's website, etc., but I think that the address space of the host PC and the address space of Qsys are different. How does the host PC access Qsys via PCI-Express and vice versa?
I'm considering PCI-Express interface for Altera's PCI-Express hard IP-equipped device. You can refer to how to build with Avalon-MM using Qsys on Altera's website, etc., but I think that the address space of the host PC and the address space of Qsys are different. How does the host PC access Qsys via PCI-Express and vice versa?
The PCI-Express (PC host) side and Qsys side have independent address spaces.
Figure 4-11 on page 4-22 of the URL link below shows the conversion table from PCI-Express address space to Avaln-MM (Qsys) address space.
https://www.altera.co.jp/ja_JP/pdfs/literature/ug/ug_pci_express.pdf
Conversely, Figure 4-12 on page 4-24 of the same document is a diagram of the conversion table of the address space from Avalon-MM to PCI-Express.
Because of the mechanism described here, it is possible to successfully exchange data in seemingly different address spaces.
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