Which signal should I check to see if the clock rx_clkout extracted from ALTGXB's CDR (Clock Data Recovery) block is stable?

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What signal should I check to see if the clock rx_clkout derived from the ALTGXB CDR (Clock Data Recovery) block is stable?

IP clock/PLL

This can be determined by the signal rx_freqlocked.

The rx_freqlocked signal is a signal that indicates the mode of the CDR block and is determined by High or Low.
High level: lock-to-data mode
Low level: lock-to-reference mode

If this signal is high, it indicates a steady state.

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