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Please tell me how to constrain sdc when applying Fast Input Register/Fast Output Register constraint.
Quartus Prime
Timing Constraints/Analysis
Even for pins set to Fast Input Register/Fast Output Register, analysis is possible if set_input_delay/output_delay constraints are described in the sdc file.
If this part is not analyzed, check if there are any constraints ignored by Report Ignored Constraints, etc., and if they are ignored, correct the ignored set_input_delay/output_delay.
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