In the "Transmitter setting" of ALTLVDS_TX, Specify phase alignment of 'tx_outclock' with respect to 'tx_out' is grayed out, but the pull-down below that says "What is the phase alignment of 'tx_outclock' with respect to 'tx_out'" is set. It seems possible. What does this setting mean?

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Specify phase alignment of 'tx_outclock' with respect to 'tx_out' is grayed out in "Transmitter setting" of ALTLVDS_TX, but the pull-down of What is the phase alignment of 'tx_outclock' with respect to 'tx_out' is set It seems that you can. What does this setting mean?

This function will be reflected only when you check "Implement Serializer/Deserializer circuit in logic cells" on the "General" tab.

For details, please refer to the user guide at the URL link below and search for the keyword "What is the phase alignment of 'tx_outclock' with respect to 'tx_out'?"
https://www.altera.com/en_US/pdfs/literature/ug/ug_altlvds.pdf

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