Yes.

The DPA function dynamically aligns the bits of received data when using a high-speed LVDS interface, so it is possible to receive data correctly without having to consider equal-length wiring between data and clock. However, it is necessary to execute the initialization sequence for proper bit alignment after reset release. Basically, multiple streams of data toggling 0,1 identify the optimal phase position for the DPA to capture the incoming data.

For details, please refer to the Device Handbook of each device from the URL link below.

For Stratix IV devices
　https://www.altera.com/en_US/pdfs/literature/hb/stratix-iv/stx4_siv54001.pdf
Please refer to P1-54 and Table 1-42 of

For Arria II GX devices
　https://www.altera.com/en_US/pdfs/literature/hb/arria-ii-gx/aiigx_53001.pdf
Please refer to P1-71, Table 1-55 of

For Stratix III devices
　https://www.altera.com/en_US/pdfs/literature/hb/stx3/stx3_siii52001.pdf
Please refer to P1-23 and Table1-26 of