In DDR3 memory interface, is it possible to perform continuous burst of 4 bursts while selecting On the fly and interfacing with BC4?

Narrow down by specifying conditions

There are currently 4341 results.

In DDR3 memory interface, is it possible to select On the fly and have 4 consecutive bursts while interfacing with BC4?

Due to the specifications of DDR3 memory devices, BC4 burst transfers cannot be continuous without a break.
An interval of at least 2 cycles occurs before the next read or write transfer.

Experienced FAE
Free consultation is available.

From specific product specifications to parts selection, the Company FAE will answer your technical concerns free of charge. Please feel free to contact us.

Inquiry form

Site Search