The reconfig_clk signal is the clock signal for dynamic reconfiguration of the transceiver blocks.

reconfig_clk must be entered even if you do not use dynamic reconfiguration of the transceiver block.
The reconfig_clk frequency range is 2.5MHz to 50MHz.
(Please note that the frequency range varies depending on the specifications of the transceiver channel.)

For details, please refer to the application note (AN558) at the URL link below.
  https://www.altera.co.jp/ja_JP/pdfs/literature/an/an558.pdf


☆ Supplementary explanation
Dynamic reconfiguration of the transceiver block is a feature that allows you to change the configuration of the transceiver block (transfer rate, protocol, analog characteristics, etc.) without reconfiguring the entire FPGA.