Category: IP (Other) / Simulation
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シミュレーターが ModelSim® の場合には、以下のエラーが発生します。
<Verilog HDL>
Error (suppressible): (vsim-10000) Unresolved defparam reference to 'lvds_rx_reg_setting' in ALTLVDS_RX_component.lvds_rx_reg_setting.

<VHDL>
Error: (vsim-3733) No default binding for component instance 'ALTLVDS_RX_component'.
The following component generic is not on the entity:
lvds_rx_reg_setting

This error occurs with the ALTLVDS_RX IP created in Quartus® Prime 19.1 and later.
Workarounds include:

<Workaround for Verilog HDL>
Add the suppress option when running vsim. (*Workaround for ModelSim only)
Example) vsim -suppress 10000
or
Remove (or comment out) the "lvds_rx_reg_setting" parameter in the generated .v for the ALTLVDS_RX IP and use it.
example)
// ALTLVDS_RX_component.lvds_rx_reg_setting = "ON",

<Workaround for VHDL>
Remove (or comment out) the following two "lvds_rx_reg_setting" parameters in the .vhd generated by the ALTLVDS_RX IP and use them.
example)
--lvds_rx_reg_setting : STRING;
When
--lvds_rx_reg_setting => "ON",

No long-term corrective action has yet been obtained for this issue.
Until then, use one of the methods above to avoid this problem.