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Intel: I would like to check if the hard processor system SPI can be connected by loopback and can be sent and received correctly. Is it possible to output the SPI interface from the Hard Processor System (HPS) and connect it on Platform Designer like Conduit?
Category: SoC FPGA
Tool: SoC EDS
Device: Cyclone® V
With Cyclone® V's HPS built-in SPI, software operation can be checked using the loopback function built into the SPI itself. Use the SRL bit of the CTRL0 register.
If you use this method, in Platform Designer for HPS, make sure the destination is FPGA instead of HPS I/O.
You can then export the signal outside of Platform Designer. Loop it back in RTL.
Exported signals can also be observed in SignalTap.
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