Intel: Where in the Minimal Preloader (MPL) is the QSPI clock value set in Qsys reflected?

SoC FPGA Platform Designer

Category: SoCs
Tools: SoC EDS
Device: Cyclone® V


alt_qspi_init()
alt_qspi_enable()
Both are functions written in alt_qspi.c.
<Drive>:\altera\15.1\embedded\ip\altera\hps\altera_hps\hwlib\src\hwmgr\alt_qspi.c

In particular, it is below l.1203 of alt_qspi.c that is changed to the QSPI clock set by Qsys.
(There is a similar description in l.1108 in alt_qspi_init, but this is the actual setting.)

alt_qspi_enable()
status = alt_qspi_baud_rate_div_set(div_bits);

Initialization by alt_qspi_init() and activation by alt_qspi_enable() are changed to values set by Qsys.


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