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Intel: Arria® 10 devices facing each other and designed for PCI-Express (PCIe) Root Port - Endpoint (using Avalon-ST interface). Is it possible to get the information of the Configuration space set to itself from the Endpoint side?
Category: PCI-Express
tool:-
Device: Arria® 10
In the PCIe system, Configuration Transaction is basically issued from the Root Port side and Configuration Read/Write is executed on the Endpoint side, but an interface called LMI is provided for debugging purposes.
(reference)
Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon®-ST Interface for PCI Express User Guide
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avst.pdf
(5.11. LMI Signals program)
This signal can be used to perform Configuration space access.
Please use this signal as Read Only.
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