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Intel: What are the considerations when configuring FPGA from Hard Processor System (HPS) when using SoC FPGA?
Category: SoCs
Tool: Quartus® Prime / SoC EDS
device:-
The HPS and FPGA are connected via ports called bridges (AXI bus or Avalon bus).
When configuring the FPGA, the bridge must be disabled once.
Also, special care should be taken regarding enabling the FPGA2SDRAM port, as noted in the Knowledge Database below.
How can I enable the FPGA2SDRAM bridge on Cyclone V SOC and Arria V SOC devices?
https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/embedded/2016/how-and-when-can-i-enable-the-fpga2sdram- bridge-on-cyclone-v-soc.html
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