Intel: Is it okay to release nPOR before inputting HPS_CLK1 on Arria® 10 SoC?

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Intel: Is it OK to release nPOR before HPS_CLK1 input on Arria® 10 SoC?

Arria SoC FPGA SoC EDS/DS-5 Clock/PLL

Category: SoCs
tool:-
Device: Arria® 10

Do not release nPOR before HPS_CLK1 input.
Since Reset Sequence changes in synchronization with Boot clk, it is necessary to release nPOR after inputting a stable clock.

Reference information
https://www.altera.com/en_US/pdfs/literature/hb/arria-10/a10_5v4.pdf
(See Reset Sequencing section.)

A minimum of 6 clk cycles is required for Cold Reset.
See the Cold Reset Assertion Sequence item in References for the subsequent transition.

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