Intel: When transferring from the FPGA side to the Hard Processor System (HPS) side using the FPGA to HPS SDRAM Interface (F2S) port, is there a way to know that the transfer has completed successfully?

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Intel: When transferring from the FPGA side to the Hard Processor System (HPS) side on the FPGA to HPS SDRAM Interface (F2S) port, is there a way to know that the transfer has completed successfully?

SoC FPGAs

Category: SoCs
Tool: Quartus® Prime / SoC EDS
Device: Cyclone® V

The F2S port has no register to know it has been used for a transfer.
If DMA is used during transfer, processing such as transfer completion interrupts, status signals such as Error, and the use of self-made components before the F2S port is required.

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