Intel: Are there any precautions when connecting to the memory controller on the Hard Processor System (HPS) side of Arria® 10, Arria® V, or Cyclone® V?

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Intel: Are there any considerations when connecting to the memory controller on the Hard Processor System (HPS) side of Arria® 10, Arria® V and Cyclone® V?

Arria SoC FPGAs

Category: SoCs
Tools: SoC EDS
Devices: Arria® 10, Arria® V, Cyclone® V

The entire 4GB area can be accessed via the FPGA-to-SDRAM bridge.
Note that there is a limit to the accessible range when referring to SDRAM directly from the CPU.

Register settings are required to refer to the first 1MB (0x00000000 to 0x000FFFFF) and the last 1GB (0xC0000000 to 0xFBFFFFFF) of SDRAM from the CPU.
The terminal 64MB (after 0xFC000000) cannot be referenced from the CPU.
(It is necessary to devise such as referencing from the FPGA side via FPGA-to-SDRAM via HPS-to-FPGA bridge.)

For details, refer to "The SDRAM Region" in the HPS Technical Reference Manual for each device.

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