Category: IP (Other)
Tools: Quartus® Prime / Quartus® II
device:-


This setting cannot be used unless the Transceiver PHY's refrence clk is equal to SLII's data rate / (SLII's transfer size* 10).
The Clock Compensation setting monitors the deviation between the reference clk and the transceiver's parallel clock (clk used in SLII) and padding to compensate for the deviation between clocks.
The choice of 100ppm or 300ppm also depends on the accuracy of the clock.

Reference information
https://www.altera.com/documentation/vgo1460114604194.html
(Search for Clock Compensation.)