When connecting SDRAM placed on the FPGA side to h2f_axi_master in Qsys, the following error occurs.

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The following error occurs when SDRAM placed on the FPGA side is connected to h2f_axi_master in Qsys.

Platform Designer SoC FPGA

<Error message>
Error: ghrd_5astfd5k3.hps_0.h2f_axi_master: ddr_emif_0.avl_0 (<start_address>..<end_address>) is outside the master's address range (0x0..0x3fffffff)

Category: SoCs
Tools: Quartus® Prime / Quartus® II
device:-

Since h2f_axi_master has a 960MB area, it is not possible to directly connect components larger than that size.
By switching the address to access using the Address Span Extender bridge IP, it is possible to handle areas of 960 MB or more.

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