Site Search

How can I increase CPU processing performance in my SoC device?

SoC FPGAs

Category: SoCs
tool:-
Device: Cyclone® V


The access overhead is high when the SoC FPGA uses working memory with external DDR3.
Therefore, the use of cache is essential to improve CPU processing performance.

The SoC FPGA L1/L2 cache latencies are:

A) L1 hit = 1 clock
B) L1 miss, L2 hit = 6 clocks (best case)
Note: The above is the latency required for 1 cache line (32 bytes)


Experienced FAE
Free consultation is available.

From specific product specifications to parts selection, the Company FAE will answer your technical concerns free of charge. Please feel free to contact us.