How do I set the priority of the SDRAM controller in Arria 10 SoC devices?

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How do I set the Priority for the SDRAM controller in Arria 10 SoC devices?

Arria SoC FPGAs

Category: SoCs
Tools: SoC EDS
Device: Arria® 10

The SDRAM access priority in Arria 10 SoC devices is determined by the SDRAM scheduler, which manages multiple master transactions to SDRAM.

See the Functional Description of the SDRAM Scheduler section in the Reference Manual.

The priority that can be set here is in the form of QoS (Quality of Service).

The default mode for FPGA-to-SDRAM access is Regular Mode, which keeps the bandwidth usage constant.

Reference: Arria 10 Hard Processor System Technical Reference Manual
https://www.altera.com/en_US/pdfs/literature/hb/arria-10/a10_5v4.pdf

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