Category: SoCs
tool:-
Device: Cyclone® V


The reason for this is thought to be that the interrupt clear processing in the interrupt handler is not in time because the software operates at high speed by enabling the cache.

For example, consider the case where the interrupt clear function IOWR_ALTERA_AVALON_PIO_EDGE_CAP(BUTTON_PIO_BASE, 0xf); is executed for the interrupt signal of the PIO module on the FPGA side.

After executing the above interrupt clear function, you may think that the interrupt ended before going to the next process, but in fact the return process is executed before the register is cleared, and as a result the interrupt handler is called twice. is called.

In this case, the interrupt clearing process is still in the process of writing through the LWHPS_FPGA (Lightweight HPS-to-FPGA) bridge. The problem can be avoided by simply adding wait processing.

As a countermeasure, please check whether the value is properly written to the corresponding address, add register readback processing, and change the handler so that the read is completed.