Category: IP
tool:
Device: Arria® V


There is no FIFO in TX Streaming in Simplex on SerialLite II.
Also, if the same clock is input to each IP of SerialLite II, all registers operate with the same clock, so there is no skew between lanes.

By checking "Enable Lane Bonding" in Custom PHY, we are only considering 500ps of channel-to-channel skew.
Also, by giving one tx_clkout output from Custom PHY as the input clock of SerialLite II, the skew is minimized.