When receiving continuous Transaction Layer Packets (TLP) from the opposite side at the shortest possible time using PCI-Express (PCIe), please tell me the timing specifications for PCIe Hard IP (HIP) from the end of the previous TLP to the start of the next TLP.

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What is the PCIe Hard IP (HIP) timing specification from the end of the previous TLP to the beginning of the next TLP when receiving the shortest consecutive Transaction Layer Packet (TLP) from the opposite side via PCI-Express (PCIe)?

PCI Express

Category: PCI-Express®
tool:-
Device: Cyclone® IV

The final number of PCIe_coreclk cycles from the end of the previous TLP (rx_st_eop output signal asserted high (rising edge)) to the beginning of the next TLP (rx_st_sop output signal asserted high (rising edge)) is 1Cycle on Coreclkout.

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