I am using the Hard Memory Controller (HMC) in a Cyclone V device to access DDRx. Sometimes the HMC avl_ready signal is deasserted or the read response is delayed. What could be the cause?

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I am accessing DDRx using a Hard Memory Controller (HMC) in a Cyclone V device. The HMC's avl_ready signal may be deasserted or the read response may be delayed, what could be the cause?

Category: External memory interface
tool:-
Device: Cyclone® V

Possible causes include the command fifo of the controller being full, or a refresh interrupting between read commands.

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